/**
 *******************************************************************************
 * @file  HC32F160.h
 * @brief Headerfile for HC32F160 series MCU
 @verbatim
   Change Logs:
   Date             Author          Notes
   2021-05-25       CDT          First version
 @endverbatim
 *******************************************************************************
 * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
 *
 * This software component is licensed by HDSC under BSD 3-Clause license
 * (the "License"); You may not use this file except in compliance with the
 * License. You may obtain a copy of the License at:
 *                    opensource.org/licenses/BSD-3-Clause
 *
 *******************************************************************************
 **/

#ifndef __HC32F160_H__
#define __HC32F160_H__

#ifdef __cplusplus
extern "C" {
#endif

/*******************************************************************************
 * Configuration of the Cortex-M0+ Processor and Core Peripherals
 ******************************************************************************/ 
#define __MPU_PRESENT             0U      /*!< HC32F160 provides no MPU                     */
#define __VTOR_PRESENT            1U      /*!< HC32F160 supported vector table registers    */
#define __NVIC_PRIO_BITS          2U      /*!< HC32F160 uses 2 Bits for the Priority Levels */
#define __Vendor_SysTickConfig    0U      /*!< Set to 1 if different SysTick Config is used */ 

/*******************************************************************************
 * Interrupt Number Definition
 ******************************************************************************/
typedef enum
{
    NMI_IRQn                  = -14, /*  2 Non Maskable                            */
    HardFault_IRQn            = -13, /*  3 Hard Fault                              */
    SVC_IRQn                  = -5,  /* 11 SVCall                                  */
    PendSV_IRQn               = -2,  /* 14 Pend SV                                 */
    SysTick_IRQn              = -1,  /* 15 System Tick                             */
    EXTINT_PORT_EIRQ0_IRQn    = 0,
    EXTINT_PORT_EIRQ1_IRQn    = 1,
    EXTINT_PORT_EIRQ2_IRQn    = 2,
    EXTINT_PORT_EIRQ3_IRQn    = 3,
    EXTINT_PORT_EIRQ4_IRQn    = 4,
    EXTINT_PORT_EIRQ5_IRQn    = 5,
    EXTINT_PORT_EIRQ6_IRQn    = 6,
    EXTINT_PORT_EIRQ7_IRQn    = 7,
    INT008_IRQn               = 8,
    INT009_IRQn               = 9,
    INT010_IRQn               = 10,
    INT011_IRQn               = 11,
    INT012_IRQn               = 12,
    INT013_IRQn               = 13,
    INT014_IRQn               = 14,
    INT015_IRQn               = 15,
    INT016_IRQn               = 16,
    INT017_IRQn               = 17,
    INT018_IRQn               = 18,
    INT019_IRQn               = 19,
    INT020_IRQn               = 20,
    INT021_IRQn               = 21,
    INT022_IRQn               = 22,
    INT023_IRQn               = 23,
    INT024_IRQn               = 24,
    INT025_IRQn               = 25,
    INT026_IRQn               = 26,
    INT027_IRQn               = 27,
    INT028_IRQn               = 28,
    INT029_IRQn               = 29,
    INT030_IRQn               = 30,
    INT031_IRQn               = 31,
} IRQn_Type;

#include <core_cm0plus.h>
#include <stdint.h>

/**
 *******************************************************************************
 ** \brief Event number enumeration
 ******************************************************************************/
typedef enum
{
    EVT_PORT_EIRQ0           = 0U,
    EVT_PORT_EIRQ8           = 1U,
    EVT_DMA_TC0              = 2U,
    EVT_DMA_BTC0             = 3U,
    EVT_TMRB_7_OVF           = 8U,
    EVT_TMRB_7_UDF           = 9U,
    EVT_TMRB_8_CMP           = 10U,
    EVT_PORT_EIRQ1           = 16U,
    EVT_PORT_EIRQ9           = 17U,
    EVT_DMA_TC1              = 18U,
    EVT_DMA_BTC1             = 19U,
    EVT_TMRB_8_VOF           = 24U,
    EVT_TMRB_8_UDF           = 25U,
    EVT_TMRB_7_CMP           = 26U,
    EVT_USART1_RI            = 28U,
    EVT_USART4_RI            = 31U,
    EVT_PORT_EIRQ2           = 32U,
    EVT_TMRB_5_OVF           = 40U,
    EVT_TMRB_5_UDF           = 41U,
    EVT_TMRB_6_CMP           = 42U,
    EVT_USART5_RI            = 43U,
    EVT_USART1_TI            = 44U,
    EVT_PORT_EIRQ3           = 48U,
    EVT_TMR0_GCMP            = 50U,
    EVT_USART6_RI            = 52U,
    EVT_TMRB_6_OVF           = 56U,
    EVT_TMRB_6_UDF           = 57U,
    EVT_TMRB_5_CMP           = 58U,
    EVT_EVENT_STRG           = 59U,
    EVT_USART3_RI            = 61U,
    EVT_SPI_SPRI             = 62U,
    EVT_PORT_EIRQ4           = 64U,
    EVT_USART5_TI            = 71U,
    EVT_TMRB_3_OVF           = 72U,
    EVT_TMRB_3_UDF           = 73U,
    EVT_TMRB_4_CMP           = 74U,
    EVT_ADC_EOCA             = 75U,
    EVT_USART3_TI            = 77U,
    EVT_PORT_EIRQ5           = 80U,
    EVT_PORT_EIRQ10          = 85U,
    EVT_USART6_TI            = 87U,
    EVT_TMRB_4_OVF           = 88U,
    EVT_TMRB_4_UDF           = 89U,
    EVT_TMRB_3_CMP           = 90U,
    EVT_ADC_EOCB             = 91U,
    EVT_USART2_RI            = 92U,
    EVT_I2C_RXI              = 94U,
    EVT_PORT_EIRQ11          = 101U,
    EVT_TMRB_1_OVF           = 104U,
    EVT_TMRB_1_UDF           = 105U,
    EVT_TMRB_2_CMP           = 106U,
    EVT_ADC_CMP0             = 107U,
    EVT_USART2_TI            = 108U,
    EVT_I2C_TXI              = 109U,
    EVT_USART4_TI            = 111U,
    EVT_PORT_QIRQ7           = 112U,
    EVT_EFM_OPTEND           = 116U,
    EVT_RTC_ALM              = 117U,
    EVT_RTC_PRD              = 118U,
    EVT_TMRB_2_OVF           = 120U,
    EVT_TMRB_2_UDF           = 121U,
    EVT_TMRB_1_CMP           = 122U,
    EVT_ADC_CMP1             = 123U,
    EVT_SPI_SPTI             = 125U,
    EVT_USART4_TCI           = 127U,
    EVT_MAX                  = 127U,
} en_event_src_t;

/**
 *******************************************************************************
 ** \brief InterrUpt nUmber enumeration
 ******************************************************************************/
typedef enum
{
    INT_PORT_EIRQ0           = 0U,
    INT_PORT_EIRQ8           = 1U,
    INT_DMA_TC0              = 2U,
    INT_DMA_BTC0             = 3U,
    INT_EFM_PEERR            = 4U,
    INT_EFM_RDCOL            = 5U,
    INT_XTAL_STOP            = 6U,
    INT_SWDT_NMIUNDF         = 7U,
    INT_TMRB_7_OVF           = 8U,
    INT_TMRB_7_UDF           = 9U,
    INT_TMRB_8_CMP           = 10U,
    INT_USART5_EI            = 11U,
    INT_USART1_EI            = 12U,
    INT_I2C_EEI              = 13U,
    INT_SPI_SPEI             = 14U,
    INT_USART4_EI            = 15U,
    INT_PORT_EIRQ1           = 16U,
    INT_PORT_EIRQ9           = 17U,
    INT_DMA_TC1              = 18U,
    INT_DMA_BTC1             = 19U,
    INT_CTC_ERR              = 20U,
    INT_TMRB_8_OVF           = 24U,
    INT_TMRB_8_UDF           = 25U,
    INT_TMRB_7_CMP           = 26U,
    INT_USART6_EI            = 27U,
    INT_USART1_RI            = 28U,
    INT_USART4_RI            = 31U,
    INT_PORT_EIRQ2           = 32U,
    INT_DMA_ERR              = 33U,
    INT_TMRB_5_OVF           = 40U,
    INT_TMRB_5_UDF           = 41U,
    INT_TMRB_6_CMP           = 42U,
    INT_USART5_RI            = 43U,
    INT_USART1_TI            = 44U,
    INT_USART3_EI            = 45U,
    INT_PORT_EIRQ3           = 48U,
    INT_PORT_EKEY            = 49U,
    INT_TMR0_GCMP            = 50U,
    INT_USART6_RI            = 51U,
    INT_TMRB_6_OVF           = 56U,
    INT_TMRB_6_UDF           = 57U,
    INT_TMRB_5_CMP           = 58U,
    INT_USART1_TCI           = 60U,
    INT_USART3_RI            = 61U,
    INT_SPI_SPRI             = 62U,
    INT_PORT_EIRQ4           = 64U,
    INT_USART5_TI            = 71U,
    INT_TMRB_3_OVF           = 72U,
    INT_TMRB_3_UDF           = 73U,
    INT_TMRB_4_CMP           = 74U,
    INT_ADC_EOCA             = 75U,
    INT_USART2_EI            = 76U,
    INT_USART3_TI            = 77U,
    INT_I2C_TEI              = 78U,
    INT_SPI_SPII             = 79U,
    INT_PORT_EIRQ5           = 80U,
    INT_PORT_EIRQ10          = 85U,
    INT_USART6_TI            = 87U,
    INT_TMRB_4_OVF           = 88U,
    INT_TMRB_4_UDF           = 89U,
    INT_TMRB_3_CMP           = 90U,
    INT_ADC_EOCB             = 91U,
    INT_USART2_RI            = 92U,
    INT_USART3_TCI           = 93U,
    INT_I2C_RXI              = 94U,
    INT_PORT_EIRQ6           = 96U,
    INT_PORT_EIRQ11          = 101U,
    INT_USART5_TCI           = 103U,
    INT_TMRB_1_OVF           = 104U,
    INT_TMRB_1_UDF           = 105U,
    INT_TMRB_2_CMP           = 106U,
    INT_ADC_CMP0             = 107U,
    INT_USART2_TI            = 108U,
    INT_I2C_TXI              = 109U,
    INT_USART4_TI            = 111U,
    INT_PORT_EIRQ7           = 112U,
    INT_LVD_DET              = 114U,
    INT_USART6_TCI           = 115U,
    INT_EFM_OPTEND           = 116U,
    INT_RTC_ALM              = 117U,
    INT_RTC_PRD              = 118U,
    INT_TMRB_2_OVF           = 120U,
    INT_TMRB_2_UDF           = 121U,
    INT_TMRB_1_CMP           = 122U,
    INT_ADC_CMP1             = 123U,
    INT_USART2_TCI           = 124U,
    INT_SPI_SPTI             = 125U,
    INT_USART4_TCI           = 127U,
    INT_MAX                  = 127U,
} en_int_src_t;  

#if defined ( __CC_ARM   )
#pragma anon_unions
#endif

/******************************************************************************/
/*                Device Specific Peripheral Registers structures             */
/******************************************************************************/

/**
 * @brief ADC
 */
typedef struct
{
    __IO uint8_t  STR;
    uint8_t RESERVED0[1];
    __IO uint16_t CR0;
    __IO uint16_t CR1;
    uint8_t RESERVED1[4];
    __IO uint16_t TRGSR;
    __IO uint16_t CHSELRA0;
    uint8_t RESERVED2[2];
    __IO uint16_t CHSELRB0;
    uint8_t RESERVED3[6];
    __IO uint8_t  EXCHSELR;
    uint8_t RESERVED4[7];
    __IO uint8_t  SSTR;
    uint8_t RESERVED5[35];
    __I  uint8_t  ISR;
    __IO uint8_t  ICR;
    __O  uint8_t  ISCLRR;
    uint8_t RESERVED6[9];
    __I  uint16_t DR0;
    __I  uint16_t DR1;
    __I  uint16_t DR2;
    __I  uint16_t DR3;
    __I  uint16_t DR4;
    __I  uint16_t DR5;
    __I  uint16_t DR6;
    __I  uint16_t DR7;
    __I  uint16_t DR8;
    __I  uint16_t DR9;
    __I  uint16_t DR10;
    __I  uint16_t DR11;
    uint8_t RESERVED7[56];
    __IO uint16_t AWDCR;
    __I  uint8_t  AWDSR;
    __O  uint8_t  AWDSCLRR;
    __IO uint16_t AWD0DR0;
    __IO uint16_t AWD0DR1;
    __IO uint8_t  AWD0CHSR;
    uint8_t RESERVED8[3];
    __IO uint16_t AWD1DR0;
    __IO uint16_t AWD1DR1;
    __IO uint8_t  AWD1CHSR;
} CM_ADC_TypeDef;

/**
 * @brief AOS
 */
typedef struct
{
    __O  uint32_t INTC_STRGCR;
    uint8_t RESERVED0[28];
    __IO uint32_t TMR0_HTSSR;
    uint8_t RESERVED1[44];
    __IO uint32_t TMRB_HTSSR;
    uint8_t RESERVED2[12];
    __IO uint32_t ADC_ITRGSELR0;
    __IO uint32_t ADC_ITRGSELR1;
    uint8_t RESERVED3[24];
    __IO uint32_t DMA0_TRGSEL;
    __IO uint32_t DMA1_TRGSEL;
} CM_AOS_TypeDef;

/**
 * @brief CMU
 */
typedef struct
{
    __IO uint8_t  PERICKSEL;
    uint8_t RESERVED0[3];
    __IO uint8_t  XTALSTDSR;
    uint8_t RESERVED1[3];
    __IO uint8_t  SCKDIVR;
    uint8_t RESERVED2[3];
    __IO uint8_t  CKSWR;
    uint8_t RESERVED3[3];
    __IO uint8_t  XTALCR;
    uint8_t RESERVED4[3];
    __IO uint8_t  XTALCFGR;
    __IO uint8_t  XTALSTBCR;
    uint8_t RESERVED5[2];
    __IO uint8_t  HRCCR;
    uint8_t RESERVED6[7];
    __I  uint8_t  OSCSTBSR;
    uint8_t RESERVED7[3];
    __IO uint8_t  MCO1CFGR;
    uint8_t RESERVED8[3];
    __IO uint8_t  XTALSTDCR;
    uint8_t RESERVED9[7];
    __IO uint32_t FCG;
    __IO uint8_t  XTAL32CR;
    uint8_t RESERVED10[3];
    __IO uint8_t  XTAL32CFGR;
    __IO uint8_t  XTAL32NFR;
    uint8_t RESERVED11[2];
    __IO uint8_t  LRCCR;
} CM_CMU_TypeDef;

/**
 * @brief CRC
 */
typedef struct
{
    __IO uint32_t CR;
    __IO uint32_t RESLT;
    uint8_t RESERVED0[120];
    __IO uint32_t DAT0;
    __IO uint32_t DAT1;
    __IO uint32_t DAT2;
    __IO uint32_t DAT3;
    __IO uint32_t DAT4;
    __IO uint32_t DAT5;
    __IO uint32_t DAT6;
    __IO uint32_t DAT7;
    __IO uint32_t DAT8;
    __IO uint32_t DAT9;
    __IO uint32_t DAT10;
    __IO uint32_t DAT11;
    __IO uint32_t DAT12;
    __IO uint32_t DAT13;
    __IO uint32_t DAT14;
    __IO uint32_t DAT15;
    __IO uint32_t DAT16;
    __IO uint32_t DAT17;
    __IO uint32_t DAT18;
    __IO uint32_t DAT19;
    __IO uint32_t DAT20;
    __IO uint32_t DAT21;
    __IO uint32_t DAT22;
    __IO uint32_t DAT23;
    __IO uint32_t DAT24;
    __IO uint32_t DAT25;
    __IO uint32_t DAT26;
    __IO uint32_t DAT27;
    __IO uint32_t DAT28;
    __IO uint32_t DAT29;
    __IO uint32_t DAT30;
    __IO uint32_t DAT31;
} CM_CRC_TypeDef;

/**
 * @brief CTC
 */
typedef struct
{
    __IO uint32_t CR1;
    __IO uint32_t CR2;
    __I  uint32_t STR;
    __I  uint16_t CNT;
} CM_CTC_TypeDef;

/**
 * @brief DBGC
 */
typedef struct
{
    __IO uint32_t MCUDBGSTAT;
    __IO uint32_t MCUSTPCTL;
} CM_DBGC_TypeDef;

/**
 * @brief DBGC_T
 */
typedef struct
{
    __IO uint32_t AUTHID0;
    __IO uint32_t AUTHID1;
    __IO uint32_t AUTHID2;
    __IO uint32_t RESV0;
    __IO uint32_t MCUSTAT;
    __IO uint32_t MCUCTL;
    __IO uint32_t FMCCTL;
} CM_DBGC_T_TypeDef;

/**
 * @brief DMA
 */
typedef struct
{
    __IO uint32_t EN;
    __I  uint32_t INTSTAT0;
    __I  uint32_t INTSTAT1;
    __IO uint32_t INTMASK0;
    __IO uint32_t INTMASK1;
    __O  uint32_t INTCLR0;
    __O  uint32_t INTCLR1;
    __IO uint32_t CHEN;
    uint8_t RESERVED0[4];
    __I  uint32_t CHSTAT;
    uint8_t RESERVED1[8];
    __IO uint32_t BASE1_LLP;
    __IO uint32_t BASE2_LLP;
    __IO uint32_t CHENCLR;
    uint8_t RESERVED2[4];
    __IO uint32_t SAR0;
    __IO uint32_t DAR0;
    __IO uint32_t CH0CTL0;
    __IO uint32_t CH0CTL1;
    uint8_t RESERVED3[48];
    __IO uint32_t SAR1;
    __IO uint32_t DAR1;
    __IO uint32_t CH1CTL0;
    __IO uint32_t CH1CTL1;
} CM_DMA_TypeDef;

/**
 * @brief EFM
 */
typedef struct
{
    __IO uint32_t FAPRT;
    __IO uint32_t FSTP;
    __IO uint32_t FRMC;
    __IO uint32_t FWMC;
    __I  uint32_t FSR;
    __IO uint32_t FSCLR;
    __IO uint32_t FITE;
    uint8_t RESERVED0[4];
    __IO uint32_t FPMTSW;
    __IO uint32_t FPMTEW;
    uint8_t RESERVED1[40];
    __I  uint32_t UQID0;
    __I  uint32_t UQID1;
    __I  uint32_t UQID2;
    uint8_t RESERVED2[550];
    __IO uint8_t  CMU_HRCCFGR;
    uint8_t RESERVED3[1];
    __IO uint16_t PWC_LVDICGCR;
} CM_EFM_TypeDef;

/**
 * @brief GPIO
 */
typedef struct
{
    __I  uint8_t  PIDR0;
    __I  uint8_t  PIDR1;
    __I  uint8_t  PIDR2;
    __I  uint8_t  PIDR3;
    __I  uint8_t  PIDR4;
    __I  uint8_t  PIDR5;
    __I  uint8_t  PIDR6;
    __I  uint8_t  PIDR7;
    uint8_t RESERVED0[4];
    __I  uint8_t  PIDR12;
    __I  uint8_t  PIDR13;
    __I  uint8_t  PIDR14;
    uint8_t RESERVED1[1];
    __IO uint8_t  PODR0;
    __IO uint8_t  PODR1;
    __IO uint8_t  PODR2;
    __IO uint8_t  PODR3;
    __IO uint8_t  PODR4;
    __IO uint8_t  PODR5;
    __IO uint8_t  PODR6;
    __IO uint8_t  PODR7;
    uint8_t RESERVED2[4];
    __IO uint8_t  PODR12;
    __IO uint8_t  PODR13;
    __IO uint8_t  PODR14;
    uint8_t RESERVED3[1];
    __IO uint8_t  POER0;
    __IO uint8_t  POER1;
    __IO uint8_t  POER2;
    __IO uint8_t  POER3;
    __IO uint8_t  POER4;
    __IO uint8_t  POER5;
    __IO uint8_t  POER6;
    __IO uint8_t  POER7;
    uint8_t RESERVED4[4];
    __IO uint8_t  POER12;
    __IO uint8_t  POER13;
    __IO uint8_t  POER14;
    uint8_t RESERVED5[1];
    __O  uint8_t  POSR0;
    __O  uint8_t  POSR1;
    __O  uint8_t  POSR2;
    __O  uint8_t  POSR3;
    __O  uint8_t  POSR4;
    __O  uint8_t  POSR5;
    __O  uint8_t  POSR6;
    __O  uint8_t  POSR7;
    uint8_t RESERVED6[4];
    __O  uint8_t  POSR12;
    __O  uint8_t  POSR13;
    __O  uint8_t  POSR14;
    uint8_t RESERVED7[1];
    __O  uint8_t  PORR0;
    __O  uint8_t  PORR1;
    __O  uint8_t  PORR2;
    __O  uint8_t  PORR3;
    __O  uint8_t  PORR4;
    __O  uint8_t  PORR5;
    __O  uint8_t  PORR6;
    __O  uint8_t  PORR7;
    uint8_t RESERVED8[4];
    __O  uint8_t  PORR12;
    __O  uint8_t  PORR13;
    __O  uint8_t  PORR14;
    uint8_t RESERVED9[1];
    __O  uint8_t  POTR0;
    __O  uint8_t  POTR1;
    __O  uint8_t  POTR2;
    __O  uint8_t  POTR3;
    __O  uint8_t  POTR4;
    __O  uint8_t  POTR5;
    __O  uint8_t  POTR6;
    __O  uint8_t  POTR7;
    uint8_t RESERVED10[4];
    __O  uint8_t  POTR12;
    __O  uint8_t  POTR13;
    __O  uint8_t  POTR14;
    uint8_t RESERVED11[929];
    __IO uint16_t PCR00;
    __IO uint16_t PCR01;
    __IO uint16_t PCR02;
    __IO uint16_t PCR03;
    __IO uint16_t PCR04;
    __IO uint16_t PCR05;
    __IO uint16_t PCR06;
    uint8_t RESERVED12[2];
    __IO uint16_t PCR10;
    __IO uint16_t PCR11;
    __IO uint16_t PCR12;
    __IO uint16_t PCR13;
    __IO uint16_t PCR14;
    __IO uint16_t PCR15;
    __IO uint16_t PCR16;
    __IO uint16_t PCR17;
    __IO uint16_t PCR20;
    __IO uint16_t PCR21;
    __IO uint16_t PCR22;
    __IO uint16_t PCR23;
    __IO uint16_t PCR24;
    __IO uint16_t PCR25;
    __IO uint16_t PCR26;
    __IO uint16_t PCR27;
    __IO uint16_t PCR30;
    __IO uint16_t PCR31;
    uint8_t RESERVED13[12];
    __IO uint16_t PCR40;
    __IO uint16_t PCR41;
    __IO uint16_t PCR42;
    __IO uint16_t PCR43;
    uint8_t RESERVED14[8];
    __IO uint16_t PCR50;
    __IO uint16_t PCR51;
    __IO uint16_t PCR52;
    __IO uint16_t PCR53;
    __IO uint16_t PCR54;
    __IO uint16_t PCR55;
    uint8_t RESERVED15[4];
    __IO uint16_t PCR60;
    __IO uint16_t PCR61;
    __IO uint16_t PCR62;
    __IO uint16_t PCR63;
    uint8_t RESERVED16[8];
    __IO uint16_t PCR70;
    __IO uint16_t PCR71;
    __IO uint16_t PCR72;
    __IO uint16_t PCR73;
    __IO uint16_t PCR74;
    __IO uint16_t PCR75;
    __IO uint16_t PCR76;
    __IO uint16_t PCR77;
    uint8_t RESERVED17[64];
    __IO uint16_t PCR120;
    __IO uint16_t PCR121;
    __IO uint16_t PCR122;
    __IO uint16_t PCR123;
    __IO uint16_t PCR124;
    uint8_t RESERVED18[6];
    __IO uint16_t PCR130;
    uint8_t RESERVED19[12];
    __IO uint16_t PCR137;
    __IO uint16_t PCR140;
    __IO uint16_t PCR141;
    uint8_t RESERVED20[8];
    __IO uint16_t PCR146;
    __IO uint16_t PCR147;
    uint8_t RESERVED21[16];
    __IO uint16_t PSPCR;
    uint8_t RESERVED22[2];
    __IO uint16_t PCCR;
    __IO uint16_t PINAER;
    __IO uint16_t PWPR;
} CM_GPIO_TypeDef;

/**
 * @brief I2C
 */
typedef struct
{
    __IO uint32_t CR1;
    __IO uint32_t CR2;
    uint8_t RESERVED0[8];
    __IO uint32_t SLR0;
    __IO uint32_t SLR1;
    uint8_t RESERVED1[4];
    __I  uint32_t SR;
    __O  uint32_t CLR;
    __IO uint8_t  DTR;
    uint8_t RESERVED2[3];
    __IO uint8_t  DRR;
    uint8_t RESERVED3[3];
    __IO uint32_t CCR;
    __IO uint32_t FLTR;
} CM_I2C_TypeDef;

/**
 * @brief ICG
 */
typedef struct
{
    __I  uint32_t ICG0;
    __I  uint32_t ICG1;
    __I  uint32_t ICG2;
    __I  uint32_t ICG3;
    __I  uint32_t ICG4;
    __I  uint32_t ICG5;
    __I  uint32_t ICG6;
} CM_ICG_TypeDef;

/**
 * @brief INTC
 */
typedef struct
{
    uint8_t RESERVED0[4];
    __IO uint32_t NMIER;
    __I  uint32_t NMIFR;
    __IO uint32_t NMICLR;
    uint8_t RESERVED1[16];
    __IO uint32_t EVTER;
    __IO uint32_t EKEYCR;
    uint8_t RESERVED2[20];
    __IO uint32_t FPRCR;
    __IO uint32_t EIRQCR0;
    __IO uint32_t EIRQCR1;
    __IO uint32_t EIRQCR2;
    __IO uint32_t EIRQCR3;
    __IO uint32_t EIRQCR4;
    __IO uint32_t EIRQCR5;
    __IO uint32_t EIRQCR6;
    __IO uint32_t EIRQCR7;
    __IO uint32_t EIRQCR8;
    __IO uint32_t EIRQCR9;
    __IO uint32_t EIRQCR10;
    __IO uint32_t EIRQCR11;
    __IO uint32_t WUPENR;
    __IO uint32_t EIRQFR;
    __IO uint32_t EIRQCLR;
    uint8_t RESERVED3[36];
    __IO uint32_t ISELAR8;
    __IO uint32_t ISELAR9;
    __IO uint32_t ISELAR10;
    __IO uint32_t ISELAR11;
    __IO uint32_t ISELAR12;
    __IO uint32_t ISELAR13;
    __IO uint32_t ISELAR14;
    __IO uint32_t ISELAR15;
    __IO uint32_t ISELAR16;
    __IO uint32_t ISELAR17;
    __IO uint32_t ISELAR18;
    __IO uint32_t ISELAR19;
    __IO uint32_t ISELAR20;
    __IO uint32_t ISELAR21;
    __IO uint32_t ISELAR22;
    __IO uint32_t ISELAR23;
    __IO uint32_t ISELBR24;
    __IO uint32_t ISELBR25;
    __IO uint32_t ISELBR26;
    __IO uint32_t ISELBR27;
    __IO uint32_t ISELBR28;
    __IO uint32_t ISELBR29;
    __IO uint32_t ISELBR30;
    __IO uint32_t ISELBR31;
} CM_INTC_TypeDef;

/**
 * @brief PWC
 */
typedef struct
{
    __IO uint8_t  STPMCR;
    uint8_t RESERVED0[3];
    __IO uint8_t  PWRC;
    uint8_t RESERVED1[3];
    __IO uint8_t  PWRMON;
    uint8_t RESERVED2[3];
    __IO uint8_t  RAMCR;
    uint8_t RESERVED3[3];
    __IO uint8_t  LVDCSR;
    uint8_t RESERVED4[15];
    __IO uint16_t FPRC;
    uint8_t RESERVED5[30];
    __IO uint8_t  DBGC;
} CM_PWC_TypeDef;

/**
 * @brief RMU
 */
typedef struct
{
    __IO uint16_t RSTF0;
} CM_RMU_TypeDef;

/**
 * @brief RTC
 */
typedef struct
{
    __IO uint8_t  CR0;
    uint8_t RESERVED0[3];
    __IO uint8_t  CR1;
    uint8_t RESERVED1[3];
    __IO uint8_t  CR2;
    uint8_t RESERVED2[3];
    __IO uint8_t  CR3;
    uint8_t RESERVED3[3];
    __IO uint8_t  SEC;
    uint8_t RESERVED4[3];
    __IO uint8_t  MIN;
    uint8_t RESERVED5[3];
    __IO uint8_t  HOUR;
    uint8_t RESERVED6[3];
    __IO uint8_t  WEEK;
    uint8_t RESERVED7[3];
    __IO uint8_t  DAY;
    uint8_t RESERVED8[3];
    __IO uint8_t  MON;
    uint8_t RESERVED9[3];
    __IO uint8_t  YEAR;
    uint8_t RESERVED10[3];
    __IO uint8_t  ALMMIN;
    uint8_t RESERVED11[3];
    __IO uint8_t  ALMHOUR;
    uint8_t RESERVED12[3];
    __IO uint8_t  ALMWEEK;
    uint8_t RESERVED13[3];
    __IO uint8_t  ERRCRH;
    uint8_t RESERVED14[3];
    __IO uint8_t  ERRCRL;
} CM_RTC_TypeDef;

/**
 * @brief SPI
 */
typedef struct
{
    __IO uint32_t DR;
    __IO uint32_t CR1;
    uint8_t RESERVED0[4];
    __IO uint32_t CFG1;
    uint8_t RESERVED1[4];
    __IO uint32_t SR;
    __IO uint32_t CFG2;
} CM_SPI_TypeDef;

/**
 * @brief SWDT
 */
typedef struct
{
    __IO uint32_t CR;
    __IO uint32_t SR;
    __IO uint32_t RR;
} CM_SWDT_TypeDef;

/**
 * @brief TMR0
 */
typedef struct
{
    __IO uint32_t CNTAR;
    uint8_t RESERVED0[4];
    __IO uint32_t CMPAR;
    uint8_t RESERVED1[4];
    __IO uint32_t BCONR;
    __IO uint32_t STFLR;
} CM_TMR0_TypeDef;

/**
 * @brief TMRB
 */
typedef struct
{
    __IO uint16_t CNTER;
    uint8_t RESERVED0[2];
    __IO uint16_t PERAR;
    uint8_t RESERVED1[58];
    __IO uint16_t CMPAR;
    uint8_t RESERVED2[62];
    __IO uint16_t BCSTR;
    uint8_t RESERVED3[2];
    __IO uint16_t HCONR;
    uint8_t RESERVED4[2];
    __IO uint16_t HCUPR;
    uint8_t RESERVED5[2];
    __IO uint16_t HCDOR;
    uint8_t RESERVED6[2];
    __IO uint16_t ICONR;
    uint8_t RESERVED7[2];
    __IO uint16_t ECONR;
    uint8_t RESERVED8[6];
    __IO uint16_t STFLR;
    uint8_t RESERVED9[98];
    __IO uint16_t CCONR;
    uint8_t RESERVED10[62];
    __IO uint16_t PCONR;
} CM_TMRB_TypeDef;

/**
 * @brief USART
 */
typedef struct
{
    __I  uint32_t SR;
    __IO uint32_t DR;
    __IO uint32_t BRR;
    __IO uint32_t CR1;
    __IO uint32_t CR2;
    __IO uint32_t CR3;
    __IO uint32_t PR;
} CM_USART_TypeDef;



/******************************************************************************/
/*           Device Specific Peripheral declaration & memory map              */
/******************************************************************************/

#define CM_ADC                               ((CM_ADC_TypeDef *)0x4000B800UL)
#define CM_AOS                               ((CM_AOS_TypeDef *)0x40000C00UL)
#define CM_CMU                               ((CM_CMU_TypeDef *)0x40014400UL)
#define CM_CRC                               ((CM_CRC_TypeDef *)0x40015400UL)
#define CM_CTC                               ((CM_CTC_TypeDef *)0x40000000UL)
#define CM_DBGC                              ((CM_DBGC_TypeDef *)0x40015000UL)
#define CM_DBGC_T                            ((CM_DBGC_T_TypeDef *)0xE0042000UL)
#define CM_DMA                               ((CM_DMA_TypeDef *)0x40013000UL)
#define CM_EFM                               ((CM_EFM_TypeDef *)0x40000800UL)
#define CM_GPIO                              ((CM_GPIO_TypeDef *)0x40013800UL)
#define CM_I2C                               ((CM_I2C_TypeDef *)0x40004800UL)
#define CM_ICG                               ((CM_ICG_TypeDef *)0x000000C0UL)
#define CM_INTC                              ((CM_INTC_TypeDef *)0x40011000UL)
#define CM_PWC                               ((CM_PWC_TypeDef *)0x40014000UL)
#define CM_RMU                               ((CM_RMU_TypeDef *)0x40014100UL)
#define CM_RTC                               ((CM_RTC_TypeDef *)0x4000D400UL)
#define CM_SPI                               ((CM_SPI_TypeDef *)0x40003800UL)
#define CM_SWDT                              ((CM_SWDT_TypeDef *)0x4000CC00UL)
#define CM_TMR0                              ((CM_TMR0_TypeDef *)0x40005800UL)
#define CM_TMRB_1                            ((CM_TMRB_TypeDef *)0x40007800UL)
#define CM_TMRB_2                            ((CM_TMRB_TypeDef *)0x40007C00UL)
#define CM_TMRB_3                            ((CM_TMRB_TypeDef *)0x40008000UL)
#define CM_TMRB_4                            ((CM_TMRB_TypeDef *)0x40008400UL)
#define CM_TMRB_5                            ((CM_TMRB_TypeDef *)0x40008800UL)
#define CM_TMRB_6                            ((CM_TMRB_TypeDef *)0x40008C00UL)
#define CM_TMRB_7                            ((CM_TMRB_TypeDef *)0x40009000UL)
#define CM_TMRB_8                            ((CM_TMRB_TypeDef *)0x40009400UL)
#define CM_USART1                            ((CM_USART_TypeDef *)0x40001800UL)
#define CM_USART2                            ((CM_USART_TypeDef *)0x40001C00UL)
#define CM_USART3                            ((CM_USART_TypeDef *)0x40002000UL)
#define CM_USART4                            ((CM_USART_TypeDef *)0x40002400UL)
#define CM_USART5                            ((CM_USART_TypeDef *)0x40002800UL)
#define CM_USART6                            ((CM_USART_TypeDef *)0x40002C00UL)


/******************************************************************************/
/*                   Peripheral Registers Bits Definition                     */
/******************************************************************************/

/*******************************************************************************
                Bit definition for Peripheral ADC
*******************************************************************************/
/*  Bit definition for ADC_STR register  */
#define ADC_STR_STRT                                   (0x01U)

/*  Bit definition for ADC_CR0 register  */
#define ADC_CR0_MS_POS                                 (0U)
#define ADC_CR0_MS                                     (0x0003U)
#define ADC_CR0_MS_0                                   (0x0001U)
#define ADC_CR0_MS_1                                   (0x0002U)
#define ADC_CR0_ACCSEL_POS                             (4U)
#define ADC_CR0_ACCSEL                                 (0x0030U)
#define ADC_CR0_ACCSEL_0                               (0x0010U)
#define ADC_CR0_ACCSEL_1                               (0x0020U)
#define ADC_CR0_CLREN_POS                              (6U)
#define ADC_CR0_CLREN                                  (0x0040U)
#define ADC_CR0_DFMT_POS                               (7U)
#define ADC_CR0_DFMT                                   (0x0080U)

/*  Bit definition for ADC_CR1 register  */
#define ADC_CR1_RSCHSEL_POS                            (2U)
#define ADC_CR1_RSCHSEL                                (0x0004U)

/*  Bit definition for ADC_TRGSR register  */
#define ADC_TRGSR_TRGSELA_POS                          (0U)
#define ADC_TRGSR_TRGSELA                              (0x0003U)
#define ADC_TRGSR_TRGSELA_0                            (0x0001U)
#define ADC_TRGSR_TRGSELA_1                            (0x0002U)
#define ADC_TRGSR_TRGENA_POS                           (7U)
#define ADC_TRGSR_TRGENA                               (0x0080U)
#define ADC_TRGSR_TRGSELB_POS                          (8U)
#define ADC_TRGSR_TRGSELB                              (0x0300U)
#define ADC_TRGSR_TRGSELB_0                            (0x0100U)
#define ADC_TRGSR_TRGSELB_1                            (0x0200U)
#define ADC_TRGSR_TRGENB_POS                           (15U)
#define ADC_TRGSR_TRGENB                               (0x8000U)

/*  Bit definition for ADC_CHSELRA0 register  */
#define ADC_CHSELRA0_CHSELA                            (0x3FFFU)

/*  Bit definition for ADC_CHSELRB0 register  */
#define ADC_CHSELRB0_CHSELB                            (0x3FFFU)

/*  Bit definition for ADC_EXCHSELR register  */
#define ADC_EXCHSELR_EXCHSEL                           (0x01U)

/*  Bit definition for ADC_SSTR register  */
#define ADC_SSTR                                       (0xFFU)

/*  Bit definition for ADC_ISR register  */
#define ADC_ISR_EOCAF_POS                              (0U)
#define ADC_ISR_EOCAF                                  (0x01U)
#define ADC_ISR_EOCBF_POS                              (1U)
#define ADC_ISR_EOCBF                                  (0x02U)

/*  Bit definition for ADC_ICR register  */
#define ADC_ICR_EOCAIEN_POS                            (0U)
#define ADC_ICR_EOCAIEN                                (0x01U)
#define ADC_ICR_EOCBIEN_POS                            (1U)
#define ADC_ICR_EOCBIEN                                (0x02U)

/*  Bit definition for ADC_ISCLRR register  */
#define ADC_ISCLRR_CLREOCAF_POS                        (0U)
#define ADC_ISCLRR_CLREOCAF                            (0x01U)
#define ADC_ISCLRR_CLREOCBF_POS                        (1U)
#define ADC_ISCLRR_CLREOCBF                            (0x02U)

/*  Bit definition for ADC_DR0 register  */
#define ADC_DR0                                        (0xFFFFU)

/*  Bit definition for ADC_DR1 register  */
#define ADC_DR1                                        (0xFFFFU)

/*  Bit definition for ADC_DR2 register  */
#define ADC_DR2                                        (0xFFFFU)

/*  Bit definition for ADC_DR3 register  */
#define ADC_DR3                                        (0xFFFFU)

/*  Bit definition for ADC_DR4 register  */
#define ADC_DR4                                        (0xFFFFU)

/*  Bit definition for ADC_DR5 register  */
#define ADC_DR5                                        (0xFFFFU)

/*  Bit definition for ADC_DR6 register  */
#define ADC_DR6                                        (0xFFFFU)

/*  Bit definition for ADC_DR7 register  */
#define ADC_DR7                                        (0xFFFFU)

/*  Bit definition for ADC_DR8 register  */
#define ADC_DR8                                        (0xFFFFU)

/*  Bit definition for ADC_DR9 register  */
#define ADC_DR9                                        (0xFFFFU)

/*  Bit definition for ADC_DR10 register  */
#define ADC_DR10                                       (0xFFFFU)

/*  Bit definition for ADC_DR11 register  */
#define ADC_DR11                                       (0xFFFFU)

/*  Bit definition for ADC_AWDCR register  */
#define ADC_AWDCR_AWD0EN_POS                           (0U)
#define ADC_AWDCR_AWD0EN                               (0x0001U)
#define ADC_AWDCR_AWD0IEN_POS                          (1U)
#define ADC_AWDCR_AWD0IEN                              (0x0002U)
#define ADC_AWDCR_AWD0MD_POS                           (2U)
#define ADC_AWDCR_AWD0MD                               (0x0004U)
#define ADC_AWDCR_AWD1EN_POS                           (4U)
#define ADC_AWDCR_AWD1EN                               (0x0010U)
#define ADC_AWDCR_AWD1IEN_POS                          (5U)
#define ADC_AWDCR_AWD1IEN                              (0x0020U)
#define ADC_AWDCR_AWD1MD_POS                           (6U)
#define ADC_AWDCR_AWD1MD                               (0x0040U)
#define ADC_AWDCR_AWDCM_POS                            (8U)
#define ADC_AWDCR_AWDCM                                (0x0300U)
#define ADC_AWDCR_AWDCM_0                              (0x0100U)
#define ADC_AWDCR_AWDCM_1                              (0x0200U)

/*  Bit definition for ADC_AWDSR register  */
#define ADC_AWDSR_AWD0F_POS                            (0U)
#define ADC_AWDSR_AWD0F                                (0x01U)
#define ADC_AWDSR_AWD1F_POS                            (1U)
#define ADC_AWDSR_AWD1F                                (0x02U)
#define ADC_AWDSR_AWDCMF_POS                           (4U)
#define ADC_AWDSR_AWDCMF                               (0x10U)

/*  Bit definition for ADC_AWDSCLRR register  */
#define ADC_AWDSCLRR_CLRAWD0F_POS                      (0U)
#define ADC_AWDSCLRR_CLRAWD0F                          (0x01U)
#define ADC_AWDSCLRR_CLRAWD1F_POS                      (1U)
#define ADC_AWDSCLRR_CLRAWD1F                          (0x02U)
#define ADC_AWDSCLRR_CLRAWDCMF_POS                     (4U)
#define ADC_AWDSCLRR_CLRAWDCMF                         (0x10U)

/*  Bit definition for ADC_AWD0DR0 register  */
#define ADC_AWD0DR0                                    (0xFFFFU)

/*  Bit definition for ADC_AWD0DR1 register  */
#define ADC_AWD0DR1                                    (0xFFFFU)

/*  Bit definition for ADC_AWD0CHSR register  */
#define ADC_AWD0CHSR_AWDCH                             (0x1FU)

/*  Bit definition for ADC_AWD1DR0 register  */
#define ADC_AWD1DR0                                    (0xFFFFU)

/*  Bit definition for ADC_AWD1DR1 register  */
#define ADC_AWD1DR1                                    (0xFFFFU)

/*  Bit definition for ADC_AWD1CHSR register  */
#define ADC_AWD1CHSR_AWDCH                             (0x1FU)

/*******************************************************************************
                Bit definition for Peripheral AOS
*******************************************************************************/
/*  Bit definition for AOS_INTC_STRGCR register  */
#define AOS_INTC_STRGCR_STRG                           (0x00000001UL)

/*  Bit definition for AOS_TMR0_HTSSR register  */
#define AOS_TMR0_HTSSR_TRGSEL                          (0x0000007FUL)

/*  Bit definition for AOS_TMRB_HTSSR register  */
#define AOS_TMRB_HTSSR_TRGSEL                          (0x0000007FUL)

/*  Bit definition for AOS_ADC_ITRGSELR0 register  */
#define AOS_ADC_ITRGSELR0_TRGSEL                       (0x0000007FUL)

/*  Bit definition for AOS_ADC_ITRGSELR1 register  */
#define AOS_ADC_ITRGSELR1_TRGSEL                       (0x0000007FUL)

/*  Bit definition for AOS_DMA0_TRGSEL register  */
#define AOS_DMA0_TRGSEL_TRGSEL                         (0x0000007FUL)

/*  Bit definition for AOS_DMA1_TRGSEL register  */
#define AOS_DMA1_TRGSEL_TRGSEL                         (0x0000007FUL)

/*******************************************************************************
                Bit definition for Peripheral CMU
*******************************************************************************/
/*  Bit definition for CMU_PERICKSEL register  */
#define CMU_PERICKSEL_PERICKSEL                        (0x07U)
#define CMU_PERICKSEL_PERICKSEL_0                      (0x01U)
#define CMU_PERICKSEL_PERICKSEL_1                      (0x02U)
#define CMU_PERICKSEL_PERICKSEL_2                      (0x04U)

/*  Bit definition for CMU_XTALSTDSR register  */
#define CMU_XTALSTDSR_XTALSTDF                         (0x01U)

/*  Bit definition for CMU_SCKDIVR register  */
#define CMU_SCKDIVR_SCKDIV                             (0x07U)
#define CMU_SCKDIVR_SCKDIV_0                           (0x01U)
#define CMU_SCKDIVR_SCKDIV_1                           (0x02U)
#define CMU_SCKDIVR_SCKDIV_2                           (0x04U)

/*  Bit definition for CMU_CKSWR register  */
#define CMU_CKSWR_CKSW                                 (0x03U)
#define CMU_CKSWR_CKSW_0                               (0x01U)
#define CMU_CKSWR_CKSW_1                               (0x02U)

/*  Bit definition for CMU_XTALCR register  */
#define CMU_XTALCR_XTALSTP                             (0x01U)

/*  Bit definition for CMU_XTALCFGR register  */
#define CMU_XTALCFGR_XTALDRV_POS                       (4U)
#define CMU_XTALCFGR_XTALDRV                           (0x30U)
#define CMU_XTALCFGR_XTALDRV_0                         (0x10U)
#define CMU_XTALCFGR_XTALDRV_1                         (0x20U)
#define CMU_XTALCFGR_XTALMS_POS                        (6U)
#define CMU_XTALCFGR_XTALMS                            (0x40U)
#define CMU_XTALCFGR_SUPDRV_POS                        (7U)
#define CMU_XTALCFGR_SUPDRV                            (0x80U)

/*  Bit definition for CMU_XTALSTBCR register  */
#define CMU_XTALSTBCR_XTALSTB                          (0x07U)
#define CMU_XTALSTBCR_XTALSTB_0                        (0x01U)
#define CMU_XTALSTBCR_XTALSTB_1                        (0x02U)
#define CMU_XTALSTBCR_XTALSTB_2                        (0x04U)

/*  Bit definition for CMU_HRCCR register  */
#define CMU_HRCCR_HRCSTP                               (0x01U)

/*  Bit definition for CMU_OSCSTBSR register  */
#define CMU_OSCSTBSR_HRCSTBF_POS                       (0U)
#define CMU_OSCSTBSR_HRCSTBF                           (0x01U)
#define CMU_OSCSTBSR_XTALSTBF_POS                      (3U)
#define CMU_OSCSTBSR_XTALSTBF                          (0x08U)
#define CMU_OSCSTBSR_XTAL32STBF_POS                    (4U)
#define CMU_OSCSTBSR_XTAL32STBF                        (0x10U)

/*  Bit definition for CMU_MCO1CFGR register  */
#define CMU_MCO1CFGR_MCO1SEL_POS                       (0U)
#define CMU_MCO1CFGR_MCO1SEL                           (0x0FU)
#define CMU_MCO1CFGR_MCO1SEL_0                         (0x01U)
#define CMU_MCO1CFGR_MCO1SEL_1                         (0x02U)
#define CMU_MCO1CFGR_MCO1SEL_2                         (0x04U)
#define CMU_MCO1CFGR_MCO1SEL_3                         (0x08U)
#define CMU_MCO1CFGR_MCO1DIV_POS                       (4U)
#define CMU_MCO1CFGR_MCO1DIV                           (0x70U)
#define CMU_MCO1CFGR_MCO1DIV_0                         (0x10U)
#define CMU_MCO1CFGR_MCO1DIV_1                         (0x20U)
#define CMU_MCO1CFGR_MCO1DIV_2                         (0x40U)
#define CMU_MCO1CFGR_MCO1EN_POS                        (7U)
#define CMU_MCO1CFGR_MCO1EN                            (0x80U)

/*  Bit definition for CMU_XTALSTDCR register  */
#define CMU_XTALSTDCR_XTALSTDIE_POS                    (0U)
#define CMU_XTALSTDCR_XTALSTDIE                        (0x01U)
#define CMU_XTALSTDCR_XTALSTDRE_POS                    (1U)
#define CMU_XTALSTDCR_XTALSTDRE                        (0x02U)
#define CMU_XTALSTDCR_XTALSTDRIS_POS                   (2U)
#define CMU_XTALSTDCR_XTALSTDRIS                       (0x04U)
#define CMU_XTALSTDCR_XTALSTDE_POS                     (7U)
#define CMU_XTALSTDCR_XTALSTDE                         (0x80U)

/*  Bit definition for CMU_FCG register  */
#define CMU_FCG_ADC_POS                                (0U)
#define CMU_FCG_ADC                                    (0x00000001UL)
#define CMU_FCG_CTC_POS                                (1U)
#define CMU_FCG_CTC                                    (0x00000002UL)
#define CMU_FCG_AOS_POS                                (4U)
#define CMU_FCG_AOS                                    (0x00000010UL)
#define CMU_FCG_DMA_POS                                (5U)
#define CMU_FCG_DMA                                    (0x00000020UL)
#define CMU_FCG_CRC_POS                                (7U)
#define CMU_FCG_CRC                                    (0x00000080UL)
#define CMU_FCG_TIMB1_POS                              (8U)
#define CMU_FCG_TIMB1                                  (0x00000100UL)
#define CMU_FCG_TIMB2_POS                              (9U)
#define CMU_FCG_TIMB2                                  (0x00000200UL)
#define CMU_FCG_TIMB3_POS                              (10U)
#define CMU_FCG_TIMB3                                  (0x00000400UL)
#define CMU_FCG_TIMB4_POS                              (11U)
#define CMU_FCG_TIMB4                                  (0x00000800UL)
#define CMU_FCG_TIMB5_POS                              (12U)
#define CMU_FCG_TIMB5                                  (0x00001000UL)
#define CMU_FCG_TIMB6_POS                              (13U)
#define CMU_FCG_TIMB6                                  (0x00002000UL)
#define CMU_FCG_TIMB7_POS                              (14U)
#define CMU_FCG_TIMB7                                  (0x00004000UL)
#define CMU_FCG_TIMB8_POS                              (15U)
#define CMU_FCG_TIMB8                                  (0x00008000UL)
#define CMU_FCG_TIM0_POS                               (16U)
#define CMU_FCG_TIM0                                   (0x00010000UL)
#define CMU_FCG_RTC_POS                                (23U)
#define CMU_FCG_RTC                                    (0x00800000UL)
#define CMU_FCG_UART1_POS                              (24U)
#define CMU_FCG_UART1                                  (0x01000000UL)
#define CMU_FCG_UART2_POS                              (25U)
#define CMU_FCG_UART2                                  (0x02000000UL)
#define CMU_FCG_UART3_POS                              (26U)
#define CMU_FCG_UART3                                  (0x04000000UL)
#define CMU_FCG_UART4_POS                              (27U)
#define CMU_FCG_UART4                                  (0x08000000UL)
#define CMU_FCG_I2C_POS                                (28U)
#define CMU_FCG_I2C                                    (0x10000000UL)
#define CMU_FCG_SPI_POS                                (29U)
#define CMU_FCG_SPI                                    (0x20000000UL)
#define CMU_FCG_UART5_POS                              (30U)
#define CMU_FCG_UART5                                  (0x40000000UL)
#define CMU_FCG_UART6_POS                              (31U)
#define CMU_FCG_UART6                                  (0x80000000UL)

/*  Bit definition for CMU_XTAL32CR register  */
#define CMU_XTAL32CR_XTAL32STP                         (0x01U)

/*  Bit definition for CMU_XTAL32CFGR register  */
#define CMU_XTAL32CFGR_XTAL32DRV                       (0x07U)
#define CMU_XTAL32CFGR_XTAL32DRV_0                     (0x01U)
#define CMU_XTAL32CFGR_XTAL32DRV_1                     (0x02U)
#define CMU_XTAL32CFGR_XTAL32DRV_2                     (0x04U)

/*  Bit definition for CMU_XTAL32NFR register  */
#define CMU_XTAL32NFR_XTAL32NF                         (0x03U)
#define CMU_XTAL32NFR_XTAL32NF_0                       (0x01U)
#define CMU_XTAL32NFR_XTAL32NF_1                       (0x02U)

/*  Bit definition for CMU_LRCCR register  */
#define CMU_LRCCR_LRCSTP                               (0x01U)

/*******************************************************************************
                Bit definition for Peripheral CRC
*******************************************************************************/
/*  Bit definition for CRC_CR register  */
#define CRC_CR_CR_POS                                  (0U)
#define CRC_CR_CR                                      (0x00000001UL)
#define CRC_CR_FLAG_POS                                (1U)
#define CRC_CR_FLAG                                    (0x00000002UL)

/*  Bit definition for CRC_RESLT register  */
#define CRC_RESLT                                      (0xFFFFFFFFUL)

/*  Bit definition for CRC_DAT0 register  */
#define CRC_DAT0                                       (0xFFFFFFFFUL)

/*  Bit definition for CRC_DAT1 register  */
#define CRC_DAT1                                       (0xFFFFFFFFUL)

/*  Bit definition for CRC_DAT2 register  */
#define CRC_DAT2                                       (0xFFFFFFFFUL)

/*  Bit definition for CRC_DAT3 register  */
#define CRC_DAT3                                       (0xFFFFFFFFUL)

/*  Bit definition for CRC_DAT4 register  */
#define CRC_DAT4                                       (0xFFFFFFFFUL)

/*  Bit definition for CRC_DAT5 register  */
#define CRC_DAT5                                       (0xFFFFFFFFUL)

/*  Bit definition for CRC_DAT6 register  */
#define CRC_DAT6                                       (0xFFFFFFFFUL)

/*  Bit definition for CRC_DAT7 register  */
#define CRC_DAT7                                       (0xFFFFFFFFUL)

/*  Bit definition for CRC_DAT8 register  */
#define CRC_DAT8                                       (0xFFFFFFFFUL)

/*  Bit definition for CRC_DAT9 register  */
#define CRC_DAT9                                       (0xFFFFFFFFUL)

/*  Bit definition for CRC_DAT10 register  */
#define CRC_DAT10                                      (0xFFFFFFFFUL)

/*  Bit definition for CRC_DAT11 register  */
#define CRC_DAT11                                      (0xFFFFFFFFUL)

/*  Bit definition for CRC_DAT12 register  */
#define CRC_DAT12                                      (0xFFFFFFFFUL)

/*  Bit definition for CRC_DAT13 register  */
#define CRC_DAT13                                      (0xFFFFFFFFUL)

/*  Bit definition for CRC_DAT14 register  */
#define CRC_DAT14                                      (0xFFFFFFFFUL)

/*  Bit definition for CRC_DAT15 register  */
#define CRC_DAT15                                      (0xFFFFFFFFUL)

/*  Bit definition for CRC_DAT16 register  */
#define CRC_DAT16                                      (0xFFFFFFFFUL)

/*  Bit definition for CRC_DAT17 register  */
#define CRC_DAT17                                      (0xFFFFFFFFUL)

/*  Bit definition for CRC_DAT18 register  */
#define CRC_DAT18                                      (0xFFFFFFFFUL)

/*  Bit definition for CRC_DAT19 register  */
#define CRC_DAT19                                      (0xFFFFFFFFUL)

/*  Bit definition for CRC_DAT20 register  */
#define CRC_DAT20                                      (0xFFFFFFFFUL)

/*  Bit definition for CRC_DAT21 register  */
#define CRC_DAT21                                      (0xFFFFFFFFUL)

/*  Bit definition for CRC_DAT22 register  */
#define CRC_DAT22                                      (0xFFFFFFFFUL)

/*  Bit definition for CRC_DAT23 register  */
#define CRC_DAT23                                      (0xFFFFFFFFUL)

/*  Bit definition for CRC_DAT24 register  */
#define CRC_DAT24                                      (0xFFFFFFFFUL)

/*  Bit definition for CRC_DAT25 register  */
#define CRC_DAT25                                      (0xFFFFFFFFUL)

/*  Bit definition for CRC_DAT26 register  */
#define CRC_DAT26                                      (0xFFFFFFFFUL)

/*  Bit definition for CRC_DAT27 register  */
#define CRC_DAT27                                      (0xFFFFFFFFUL)

/*  Bit definition for CRC_DAT28 register  */
#define CRC_DAT28                                      (0xFFFFFFFFUL)

/*  Bit definition for CRC_DAT29 register  */
#define CRC_DAT29                                      (0xFFFFFFFFUL)

/*  Bit definition for CRC_DAT30 register  */
#define CRC_DAT30                                      (0xFFFFFFFFUL)

/*  Bit definition for CRC_DAT31 register  */
#define CRC_DAT31                                      (0xFFFFFFFFUL)

/*******************************************************************************
                Bit definition for Peripheral CTC
*******************************************************************************/
/*  Bit definition for CTC_CR1 register  */
#define CTC_CR1_REFPSC_POS                             (0U)
#define CTC_CR1_REFPSC                                 (0x00000007UL)
#define CTC_CR1_REFPSC_0                               (0x00000001UL)
#define CTC_CR1_REFPSC_1                               (0x00000002UL)
#define CTC_CR1_REFPSC_2                               (0x00000004UL)
#define CTC_CR1_REFCKS_POS                             (4U)
#define CTC_CR1_REFCKS                                 (0x00000030UL)
#define CTC_CR1_REFCKS_0                               (0x00000010UL)
#define CTC_CR1_REFCKS_1                               (0x00000020UL)
#define CTC_CR1_ERRIE_POS                              (6U)
#define CTC_CR1_ERRIE                                  (0x00000040UL)
#define CTC_CR1_CTCEN_POS                              (7U)
#define CTC_CR1_CTCEN                                  (0x00000080UL)
#define CTC_CR1_HRCPSC_POS                             (8U)
#define CTC_CR1_HRCPSC                                 (0x00000700UL)
#define CTC_CR1_HRCPSC_0                               (0x00000100UL)
#define CTC_CR1_HRCPSC_1                               (0x00000200UL)
#define CTC_CR1_HRCPSC_2                               (0x00000400UL)
#define CTC_CR1_REFEDG_POS                             (12U)
#define CTC_CR1_REFEDG                                 (0x00003000UL)
#define CTC_CR1_REFEDG_0                               (0x00001000UL)
#define CTC_CR1_REFEDG_1                               (0x00002000UL)
#define CTC_CR1_TRMVAL_POS                             (16U)
#define CTC_CR1_TRMVAL                                 (0x003F0000UL)

/*  Bit definition for CTC_CR2 register  */
#define CTC_CR2_OFSVAL_POS                             (0U)
#define CTC_CR2_OFSVAL                                 (0x000000FFUL)
#define CTC_CR2_RLDVAL_POS                             (16U)
#define CTC_CR2_RLDVAL                                 (0xFFFF0000UL)

/*  Bit definition for CTC_STR register  */
#define CTC_STR_TRIMSUC_POS                            (0U)
#define CTC_STR_TRIMSUC                                (0x00000001UL)
#define CTC_STR_TRMOVF_POS                             (1U)
#define CTC_STR_TRMOVF                                 (0x00000002UL)
#define CTC_STR_TRMUDF_POS                             (2U)
#define CTC_STR_TRMUDF                                 (0x00000004UL)
#define CTC_STR_CTCBSY_POS                             (3U)
#define CTC_STR_CTCBSY                                 (0x00000008UL)

/*  Bit definition for CTC_CNT register  */
#define CTC_CNT_CTCCNT                                 (0xFFFFU)

/*******************************************************************************
                Bit definition for Peripheral DBGC
*******************************************************************************/
/*  Bit definition for DBGC_MCUDBGSTAT register  */
#define DBGC_MCUDBGSTAT_CDBGPWRUPREQ_POS               (0U)
#define DBGC_MCUDBGSTAT_CDBGPWRUPREQ                   (0x00000001UL)
#define DBGC_MCUDBGSTAT_CDBGPWRUPACK_POS               (1U)
#define DBGC_MCUDBGSTAT_CDBGPWRUPACK                   (0x00000002UL)

/*  Bit definition for DBGC_MCUSTPCTL register  */
#define DBGC_MCUSTPCTL_SWDTSTP_POS                     (0U)
#define DBGC_MCUSTPCTL_SWDTSTP                         (0x00000001UL)
#define DBGC_MCUSTPCTL_RTCSTP_POS                      (2U)
#define DBGC_MCUSTPCTL_RTCSTP                          (0x00000004UL)
#define DBGC_MCUSTPCTL_PVDSTP_POS                      (3U)
#define DBGC_MCUSTPCTL_PVDSTP                          (0x00000008UL)
#define DBGC_MCUSTPCTL_TMR01STP_POS                    (14U)
#define DBGC_MCUSTPCTL_TMR01STP                        (0x00004000UL)
#define DBGC_MCUSTPCTL_TMRB1STP_POS                    (24U)
#define DBGC_MCUSTPCTL_TMRB1STP                        (0x01000000UL)
#define DBGC_MCUSTPCTL_TMRB2STP_POS                    (25U)
#define DBGC_MCUSTPCTL_TMRB2STP                        (0x02000000UL)
#define DBGC_MCUSTPCTL_TMRB3STP_POS                    (26U)
#define DBGC_MCUSTPCTL_TMRB3STP                        (0x04000000UL)
#define DBGC_MCUSTPCTL_TMRB4STP_POS                    (27U)
#define DBGC_MCUSTPCTL_TMRB4STP                        (0x08000000UL)
#define DBGC_MCUSTPCTL_TMRB5STP_POS                    (28U)
#define DBGC_MCUSTPCTL_TMRB5STP                        (0x10000000UL)
#define DBGC_MCUSTPCTL_TMRB6STP_POS                    (29U)
#define DBGC_MCUSTPCTL_TMRB6STP                        (0x20000000UL)
#define DBGC_MCUSTPCTL_TMRB7STP_POS                    (30U)
#define DBGC_MCUSTPCTL_TMRB7STP                        (0x40000000UL)
#define DBGC_MCUSTPCTL_TMRB8STP_POS                    (31U)
#define DBGC_MCUSTPCTL_TMRB8STP                        (0x80000000UL)

/*******************************************************************************
                Bit definition for Peripheral DBGC_T
*******************************************************************************/
/*  Bit definition for DBGC_T_AUTHID0 register  */
#define DBGC_T_AUTHID0                                 (0xFFFFFFFFUL)

/*  Bit definition for DBGC_T_AUTHID1 register  */
#define DBGC_T_AUTHID1                                 (0xFFFFFFFFUL)

/*  Bit definition for DBGC_T_AUTHID2 register  */
#define DBGC_T_AUTHID2                                 (0xFFFFFFFFUL)

/*  Bit definition for DBGC_T_RESV0 register  */
#define DBGC_T_RESV0                                   (0xFFFFFFFFUL)

/*  Bit definition for DBGC_T_MCUSTAT register  */
#define DBGC_T_MCUSTAT_AUTH_POS                        (0U)
#define DBGC_T_MCUSTAT_AUTH                            (0x00000001UL)
#define DBGC_T_MCUSTAT_REMVLOCK_POS                    (1U)
#define DBGC_T_MCUSTAT_REMVLOCK                        (0x00000002UL)
#define DBGC_T_MCUSTAT_SAFTYLOCK1_POS                  (2U)
#define DBGC_T_MCUSTAT_SAFTYLOCK1                      (0x00000004UL)
#define DBGC_T_MCUSTAT_SAFTYLOCK2_POS                  (3U)
#define DBGC_T_MCUSTAT_SAFTYLOCK2                      (0x00000008UL)
#define DBGC_T_MCUSTAT_MCUSTAT0_POS                    (8U)
#define DBGC_T_MCUSTAT_MCUSTAT0                        (0x00000100UL)
#define DBGC_T_MCUSTAT_MCUSTAT1_POS                    (9U)
#define DBGC_T_MCUSTAT_MCUSTAT1                        (0x00000200UL)

/*  Bit definition for DBGC_T_MCUCTL register  */
#define DBGC_T_MCUCTL_EDBGRQ_POS                       (0U)
#define DBGC_T_MCUCTL_EDBGRQ                           (0x00000001UL)
#define DBGC_T_MCUCTL_RESTART_POS                      (1U)
#define DBGC_T_MCUCTL_RESTART                          (0x00000002UL)
#define DBGC_T_MCUCTL_DIRQ_POS                         (8U)
#define DBGC_T_MCUCTL_DIRQ                             (0x00000100UL)

/*  Bit definition for DBGC_T_FMCCTL register  */
#define DBGC_T_FMCCTL_ERASEREQ_POS                     (0U)
#define DBGC_T_FMCCTL_ERASEREQ                         (0x00000001UL)
#define DBGC_T_FMCCTL_ERASEACK_POS                     (1U)
#define DBGC_T_FMCCTL_ERASEACK                         (0x00000002UL)
#define DBGC_T_FMCCTL_ERASEERR_POS                     (2U)
#define DBGC_T_FMCCTL_ERASEERR                         (0x00000004UL)

/*******************************************************************************
                Bit definition for Peripheral DMA
*******************************************************************************/
/*  Bit definition for DMA_EN register  */
#define DMA_EN_EN                                      (0x00000001UL)

/*  Bit definition for DMA_INTSTAT0 register  */
#define DMA_INTSTAT0_TRNERR_POS                        (0U)
#define DMA_INTSTAT0_TRNERR                            (0x00000003UL)
#define DMA_INTSTAT0_TRNERR_0                          (0x00000001UL)
#define DMA_INTSTAT0_TRNERR_1                          (0x00000002UL)
#define DMA_INTSTAT0_REQERR_POS                        (16U)
#define DMA_INTSTAT0_REQERR                            (0x00030000UL)
#define DMA_INTSTAT0_REQERR_0                          (0x00010000UL)
#define DMA_INTSTAT0_REQERR_1                          (0x00020000UL)

/*  Bit definition for DMA_INTSTAT1 register  */
#define DMA_INTSTAT1_TC_POS                            (0U)
#define DMA_INTSTAT1_TC                                (0x00000003UL)
#define DMA_INTSTAT1_TC_0                              (0x00000001UL)
#define DMA_INTSTAT1_TC_1                              (0x00000002UL)
#define DMA_INTSTAT1_BTC_POS                           (16U)
#define DMA_INTSTAT1_BTC                               (0x00030000UL)
#define DMA_INTSTAT1_BTC_0                             (0x00010000UL)
#define DMA_INTSTAT1_BTC_1                             (0x00020000UL)

/*  Bit definition for DMA_INTMASK0 register  */
#define DMA_INTMASK0_MSKTRNERR_POS                     (0U)
#define DMA_INTMASK0_MSKTRNERR                         (0x00000003UL)
#define DMA_INTMASK0_MSKTRNERR_0                       (0x00000001UL)
#define DMA_INTMASK0_MSKTRNERR_1                       (0x00000002UL)
#define DMA_INTMASK0_MSKREQERR_POS                     (16U)
#define DMA_INTMASK0_MSKREQERR                         (0x00030000UL)
#define DMA_INTMASK0_MSKREQERR_0                       (0x00010000UL)
#define DMA_INTMASK0_MSKREQERR_1                       (0x00020000UL)

/*  Bit definition for DMA_INTMASK1 register  */
#define DMA_INTMASK1_MSKTC_POS                         (0U)
#define DMA_INTMASK1_MSKTC                             (0x00000003UL)
#define DMA_INTMASK1_MSKTC_0                           (0x00000001UL)
#define DMA_INTMASK1_MSKTC_1                           (0x00000002UL)
#define DMA_INTMASK1_MSKBTC_POS                        (16U)
#define DMA_INTMASK1_MSKBTC                            (0x00030000UL)
#define DMA_INTMASK1_MSKBTC_0                          (0x00010000UL)
#define DMA_INTMASK1_MSKBTC_1                          (0x00020000UL)

/*  Bit definition for DMA_INTCLR0 register  */
#define DMA_INTCLR0_CLRTRNERR_POS                      (0U)
#define DMA_INTCLR0_CLRTRNERR                          (0x00000003UL)
#define DMA_INTCLR0_CLRTRNERR_0                        (0x00000001UL)
#define DMA_INTCLR0_CLRTRNERR_1                        (0x00000002UL)
#define DMA_INTCLR0_CLRREQERR_POS                      (16U)
#define DMA_INTCLR0_CLRREQERR                          (0x00030000UL)
#define DMA_INTCLR0_CLRREQERR_0                        (0x00010000UL)
#define DMA_INTCLR0_CLRREQERR_1                        (0x00020000UL)

/*  Bit definition for DMA_INTCLR1 register  */
#define DMA_INTCLR1_CLRTC_POS                          (0U)
#define DMA_INTCLR1_CLRTC                              (0x00000003UL)
#define DMA_INTCLR1_CLRTC_0                            (0x00000001UL)
#define DMA_INTCLR1_CLRTC_1                            (0x00000002UL)
#define DMA_INTCLR1_CLRBTC_POS                         (16U)
#define DMA_INTCLR1_CLRBTC                             (0x00030000UL)
#define DMA_INTCLR1_CLRBTC_0                           (0x00010000UL)
#define DMA_INTCLR1_CLRBTC_1                           (0x00020000UL)

/*  Bit definition for DMA_CHEN register  */
#define DMA_CHEN_CHEN                                  (0x00000003UL)
#define DMA_CHEN_CHEN_0                                (0x00000001UL)
#define DMA_CHEN_CHEN_1                                (0x00000002UL)

/*  Bit definition for DMA_CHSTAT register  */
#define DMA_CHSTAT_DMAACT_POS                          (0U)
#define DMA_CHSTAT_DMAACT                              (0x00000001UL)
#define DMA_CHSTAT_CHACT_POS                           (16U)
#define DMA_CHSTAT_CHACT                               (0x00030000UL)
#define DMA_CHSTAT_CHACT_0                             (0x00010000UL)
#define DMA_CHSTAT_CHACT_1                             (0x00020000UL)

/*  Bit definition for DMA_BASE1_LLP register  */
#define DMA_BASE1_LLP_LLP_POS                          (14U)
#define DMA_BASE1_LLP_LLP                              (0xFFFFC000UL)

/*  Bit definition for DMA_BASE2_LLP register  */
#define DMA_BASE2_LLP_LLP_POS                          (14U)
#define DMA_BASE2_LLP_LLP                              (0xFFFFC000UL)

/*  Bit definition for DMA_CHENCLR register  */
#define DMA_CHENCLR_CHENCLR                            (0x00000003UL)
#define DMA_CHENCLR_CHENCLR_0                          (0x00000001UL)
#define DMA_CHENCLR_CHENCLR_1                          (0x00000002UL)

/*  Bit definition for DMA_SAR register  */
#define DMA_SAR                                        (0xFFFFFFFFUL)

/*  Bit definition for DMA_DAR register  */
#define DMA_DAR                                        (0xFFFFFFFFUL)

/*  Bit definition for DMA_CH0CTL0 register  */
#define DMA_CH0CTL0_BLKSIZE_POS                        (0U)
#define DMA_CH0CTL0_BLKSIZE                            (0x000000FFUL)
#define DMA_CH0CTL0_CNT_POS                            (8U)
#define DMA_CH0CTL0_CNT                                (0x0003FF00UL)
#define DMA_CH0CTL0_LLP_POS                            (18U)
#define DMA_CH0CTL0_LLP                                (0x0FFC0000UL)
#define DMA_CH0CTL0_LLPEN_POS                          (28U)
#define DMA_CH0CTL0_LLPEN                              (0x10000000UL)
#define DMA_CH0CTL0_LLPRUN_POS                         (29U)
#define DMA_CH0CTL0_LLPRUN                             (0x20000000UL)
#define DMA_CH0CTL0_HSIZE_POS                          (30U)
#define DMA_CH0CTL0_HSIZE                              (0xC0000000UL)
#define DMA_CH0CTL0_HSIZE_0                            (0x40000000UL)
#define DMA_CH0CTL0_HSIZE_1                            (0x80000000UL)

/*  Bit definition for DMA_CH0CTL1 register  */
#define DMA_CH0CTL1_OFFSET_POS                         (0U)
#define DMA_CH0CTL1_OFFSET                             (0x0000FFFFUL)
#define DMA_CH0CTL1_RPTNSCNT_POS                       (16U)
#define DMA_CH0CTL1_RPTNSCNT                           (0x00FF0000UL)
#define DMA_CH0CTL1_RPTNSEN_POS                        (24U)
#define DMA_CH0CTL1_RPTNSEN                            (0x01000000UL)
#define DMA_CH0CTL1_RPTNSSEL_POS                       (25U)
#define DMA_CH0CTL1_RPTNSSEL                           (0x06000000UL)
#define DMA_CH0CTL1_RPTNSSEL_0                         (0x02000000UL)
#define DMA_CH0CTL1_RPTNSSEL_1                         (0x04000000UL)
#define DMA_CH0CTL1_LLPSEL_POS                         (27U)
#define DMA_CH0CTL1_LLPSEL                             (0x08000000UL)
#define DMA_CH0CTL1_SINC_POS                           (28U)
#define DMA_CH0CTL1_SINC                               (0x30000000UL)
#define DMA_CH0CTL1_SINC_0                             (0x10000000UL)
#define DMA_CH0CTL1_SINC_1                             (0x20000000UL)
#define DMA_CH0CTL1_DINC_POS                           (30U)
#define DMA_CH0CTL1_DINC                               (0xC0000000UL)
#define DMA_CH0CTL1_DINC_0                             (0x40000000UL)
#define DMA_CH0CTL1_DINC_1                             (0x80000000UL)

/*  Bit definition for DMA_CH1CTL0 register  */
#define DMA_CH1CTL0_BLKSIZE_POS                        (0U)
#define DMA_CH1CTL0_BLKSIZE                            (0x000000FFUL)
#define DMA_CH1CTL0_CNT_POS                            (8U)
#define DMA_CH1CTL0_CNT                                (0x0003FF00UL)
#define DMA_CH1CTL0_LLP_POS                            (18U)
#define DMA_CH1CTL0_LLP                                (0x0FFC0000UL)
#define DMA_CH1CTL0_LLPEN_POS                          (28U)
#define DMA_CH1CTL0_LLPEN                              (0x10000000UL)
#define DMA_CH1CTL0_LLPRUN_POS                         (29U)
#define DMA_CH1CTL0_LLPRUN                             (0x20000000UL)
#define DMA_CH1CTL0_HSIZE_POS                          (30U)
#define DMA_CH1CTL0_HSIZE                              (0xC0000000UL)
#define DMA_CH1CTL0_HSIZE_0                            (0x40000000UL)
#define DMA_CH1CTL0_HSIZE_1                            (0x80000000UL)

/*  Bit definition for DMA_CH1CTL1 register  */
#define DMA_CH1CTL1_OFFSET_POS                         (0U)
#define DMA_CH1CTL1_OFFSET                             (0x0000FFFFUL)
#define DMA_CH1CTL1_RPTNSCNT_POS                       (16U)
#define DMA_CH1CTL1_RPTNSCNT                           (0x00FF0000UL)
#define DMA_CH1CTL1_RPTNSEN_POS                        (24U)
#define DMA_CH1CTL1_RPTNSEN                            (0x01000000UL)
#define DMA_CH1CTL1_RPTNSSEL_POS                       (25U)
#define DMA_CH1CTL1_RPTNSSEL                           (0x06000000UL)
#define DMA_CH1CTL1_RPTNSSEL_0                         (0x02000000UL)
#define DMA_CH1CTL1_RPTNSSEL_1                         (0x04000000UL)
#define DMA_CH1CTL1_LLPSEL_POS                         (27U)
#define DMA_CH1CTL1_LLPSEL                             (0x08000000UL)
#define DMA_CH1CTL1_SINC_POS                           (28U)
#define DMA_CH1CTL1_SINC                               (0x30000000UL)
#define DMA_CH1CTL1_SINC_0                             (0x10000000UL)
#define DMA_CH1CTL1_SINC_1                             (0x20000000UL)
#define DMA_CH1CTL1_DINC_POS                           (30U)
#define DMA_CH1CTL1_DINC                               (0xC0000000UL)
#define DMA_CH1CTL1_DINC_0                             (0x40000000UL)
#define DMA_CH1CTL1_DINC_1                             (0x80000000UL)

/*******************************************************************************
                Bit definition for Peripheral EFM
*******************************************************************************/
/*  Bit definition for EFM_FAPRT register  */
#define EFM_FAPRT_FAPRT                                (0x0000FFFFUL)

/*  Bit definition for EFM_FSTP register  */
#define EFM_FSTP_FSTP                                  (0x00000001UL)

/*  Bit definition for EFM_FRMC register  */
#define EFM_FRMC_FLWT_POS                              (0U)
#define EFM_FRMC_FLWT                                  (0x00000003UL)
#define EFM_FRMC_FLWT_0                                (0x00000001UL)
#define EFM_FRMC_FLWT_1                                (0x00000002UL)
#define EFM_FRMC_PREFETE_POS                           (17U)
#define EFM_FRMC_PREFETE                               (0x00020000UL)

/*  Bit definition for EFM_FWMC register  */
#define EFM_FWMC_PEMODE_POS                            (0U)
#define EFM_FWMC_PEMODE                                (0x00000001UL)
#define EFM_FWMC_PEMOD_POS                             (4U)
#define EFM_FWMC_PEMOD                                 (0x00000070UL)
#define EFM_FWMC_PEMOD_0                               (0x00000010UL)
#define EFM_FWMC_PEMOD_1                               (0x00000020UL)
#define EFM_FWMC_PEMOD_2                               (0x00000040UL)
#define EFM_FWMC_BUSHLDCTL_POS                         (8U)
#define EFM_FWMC_BUSHLDCTL                             (0x00000100UL)
#define EFM_FWMC_ERCALE_POS                            (16U)
#define EFM_FWMC_ERCALE                                (0x00010000UL)

/*  Bit definition for EFM_FSR register  */
#define EFM_FSR_PEWERR_POS                             (0U)
#define EFM_FSR_PEWERR                                 (0x00000001UL)
#define EFM_FSR_PEPRTERR_POS                           (1U)
#define EFM_FSR_PEPRTERR                               (0x00000002UL)
#define EFM_FSR_PGMISMTCH_POS                          (3U)
#define EFM_FSR_PGMISMTCH                              (0x00000008UL)
#define EFM_FSR_OPTEND_POS                             (4U)
#define EFM_FSR_OPTEND                                 (0x00000010UL)
#define EFM_FSR_COLERR_POS                             (5U)
#define EFM_FSR_COLERR                                 (0x00000020UL)
#define EFM_FSR_ERCAL_POS                              (6U)
#define EFM_FSR_ERCAL                                  (0x00000040UL)
#define EFM_FSR_RDY_POS                                (8U)
#define EFM_FSR_RDY                                    (0x00000100UL)

/*  Bit definition for EFM_FSCLR register  */
#define EFM_FSCLR_PEWERRCLR_POS                        (0U)
#define EFM_FSCLR_PEWERRCLR                            (0x00000001UL)
#define EFM_FSCLR_PEPRTERRCLR_POS                      (1U)
#define EFM_FSCLR_PEPRTERRCLR                          (0x00000002UL)
#define EFM_FSCLR_PGMISMTCHCLR_POS                     (3U)
#define EFM_FSCLR_PGMISMTCHCLR                         (0x00000008UL)
#define EFM_FSCLR_OPTENDCLR_POS                        (4U)
#define EFM_FSCLR_OPTENDCLR                            (0x00000010UL)
#define EFM_FSCLR_COLERRCLR_POS                        (5U)
#define EFM_FSCLR_COLERRCLR                            (0x00000020UL)
#define EFM_FSCLR_ERCALCLR_POS                         (6U)
#define EFM_FSCLR_ERCALCLR                             (0x00000040UL)

/*  Bit definition for EFM_FITE register  */
#define EFM_FITE_PEERRITE_POS                          (0U)
#define EFM_FITE_PEERRITE                              (0x00000001UL)
#define EFM_FITE_OPTENDITE_POS                         (1U)
#define EFM_FITE_OPTENDITE                             (0x00000002UL)
#define EFM_FITE_COLERRITE_POS                         (2U)
#define EFM_FITE_COLERRITE                             (0x00000004UL)

/*  Bit definition for EFM_FPMTSW register  */
#define EFM_FPMTSW_FPMTSW                              (0x0003FFFFUL)

/*  Bit definition for EFM_FPMTEW register  */
#define EFM_FPMTEW_FPMTEW                              (0x0003FFFFUL)

/*  Bit definition for EFM_UQID0 register  */
#define EFM_UQID0                                      (0xFFFFFFFFUL)

/*  Bit definition for EFM_UQID1 register  */
#define EFM_UQID1                                      (0xFFFFFFFFUL)

/*  Bit definition for EFM_UQID2 register  */
#define EFM_UQID2                                      (0xFFFFFFFFUL)

/*  Bit definition for EFM_CMU_HRCCFGR register  */
#define EFM_CMU_HRCCFGR_HRCFREQS                       (0x0FU)
#define EFM_CMU_HRCCFGR_HRCFREQS_0                     (0x01U)
#define EFM_CMU_HRCCFGR_HRCFREQS_1                     (0x02U)
#define EFM_CMU_HRCCFGR_HRCFREQS_2                     (0x04U)
#define EFM_CMU_HRCCFGR_HRCFREQS_3                     (0x08U)

/*  Bit definition for EFM_PWC_LVDICGCR register  */
#define EFM_PWC_LVDICGCR_DFS_POS                       (0U)
#define EFM_PWC_LVDICGCR_DFS                           (0x0003U)
#define EFM_PWC_LVDICGCR_DFS_0                         (0x0001U)
#define EFM_PWC_LVDICGCR_DFS_1                         (0x0002U)
#define EFM_PWC_LVDICGCR_DFDIS_POS                     (2U)
#define EFM_PWC_LVDICGCR_DFDIS                         (0x0004U)
#define EFM_PWC_LVDICGCR_LVDLVL_POS                    (8U)
#define EFM_PWC_LVDICGCR_LVDLVL                        (0x0F00U)
#define EFM_PWC_LVDICGCR_LVDLVL_0                      (0x0100U)
#define EFM_PWC_LVDICGCR_LVDLVL_1                      (0x0200U)
#define EFM_PWC_LVDICGCR_LVDLVL_2                      (0x0400U)
#define EFM_PWC_LVDICGCR_LVDLVL_3                      (0x0800U)
#define EFM_PWC_LVDICGCR_NMIS_POS                      (12U)
#define EFM_PWC_LVDICGCR_NMIS                          (0x1000U)
#define EFM_PWC_LVDICGCR_IRS_POS                       (13U)
#define EFM_PWC_LVDICGCR_IRS                           (0x2000U)
#define EFM_PWC_LVDICGCR_IRDIS_POS                     (14U)
#define EFM_PWC_LVDICGCR_IRDIS                         (0x4000U)
#define EFM_PWC_LVDICGCR_LVDDIS_POS                    (15U)
#define EFM_PWC_LVDICGCR_LVDDIS                        (0x8000U)

/*******************************************************************************
                Bit definition for Peripheral GPIO
*******************************************************************************/
/*  Bit definition for GPIO_PIDR register  */
#define GPIO_PIDR_PIN0_POS                             (0U)
#define GPIO_PIDR_PIN0                                 (0x01U)
#define GPIO_PIDR_PIN1_POS                             (1U)
#define GPIO_PIDR_PIN1                                 (0x02U)
#define GPIO_PIDR_PIN2_POS                             (2U)
#define GPIO_PIDR_PIN2                                 (0x04U)
#define GPIO_PIDR_PIN3_POS                             (3U)
#define GPIO_PIDR_PIN3                                 (0x08U)
#define GPIO_PIDR_PIN4_POS                             (4U)
#define GPIO_PIDR_PIN4                                 (0x10U)
#define GPIO_PIDR_PIN5_POS                             (5U)
#define GPIO_PIDR_PIN5                                 (0x20U)
#define GPIO_PIDR_PIN6_POS                             (6U)
#define GPIO_PIDR_PIN6                                 (0x40U)
#define GPIO_PIDR_PIN7_POS                             (7U)
#define GPIO_PIDR_PIN7                                 (0x80U)

/*  Bit definition for GPIO_PODR register  */
#define GPIO_PODR_POUT0_POS                            (0U)
#define GPIO_PODR_POUT0                                (0x01U)
#define GPIO_PODR_POUT1_POS                            (1U)
#define GPIO_PODR_POUT1                                (0x02U)
#define GPIO_PODR_POUT2_POS                            (2U)
#define GPIO_PODR_POUT2                                (0x04U)
#define GPIO_PODR_POUT3_POS                            (3U)
#define GPIO_PODR_POUT3                                (0x08U)
#define GPIO_PODR_POUT4_POS                            (4U)
#define GPIO_PODR_POUT4                                (0x10U)
#define GPIO_PODR_POUT5_POS                            (5U)
#define GPIO_PODR_POUT5                                (0x20U)
#define GPIO_PODR_POUT6_POS                            (6U)
#define GPIO_PODR_POUT6                                (0x40U)
#define GPIO_PODR_POUT7_POS                            (7U)
#define GPIO_PODR_POUT7                                (0x80U)

/*  Bit definition for GPIO_POER register  */
#define GPIO_POER_POUTE0_POS                           (0U)
#define GPIO_POER_POUTE0                               (0x01U)
#define GPIO_POER_POUTE1_POS                           (1U)
#define GPIO_POER_POUTE1                               (0x02U)
#define GPIO_POER_POUTE2_POS                           (2U)
#define GPIO_POER_POUTE2                               (0x04U)
#define GPIO_POER_POUTE3_POS                           (3U)
#define GPIO_POER_POUTE3                               (0x08U)
#define GPIO_POER_POUTE4_POS                           (4U)
#define GPIO_POER_POUTE4                               (0x10U)
#define GPIO_POER_POUTE5_POS                           (5U)
#define GPIO_POER_POUTE5                               (0x20U)
#define GPIO_POER_POUTE6_POS                           (6U)
#define GPIO_POER_POUTE6                               (0x40U)
#define GPIO_POER_POUTE7_POS                           (7U)
#define GPIO_POER_POUTE7                               (0x80U)

/*  Bit definition for GPIO_POSR register  */
#define GPIO_POSR_POS0_POS                             (0U)
#define GPIO_POSR_POS0                                 (0x01U)
#define GPIO_POSR_POS1_POS                             (1U)
#define GPIO_POSR_POS1                                 (0x02U)
#define GPIO_POSR_POS2_POS                             (2U)
#define GPIO_POSR_POS2                                 (0x04U)
#define GPIO_POSR_POS3_POS                             (3U)
#define GPIO_POSR_POS3                                 (0x08U)
#define GPIO_POSR_POS4_POS                             (4U)
#define GPIO_POSR_POS4                                 (0x10U)
#define GPIO_POSR_POS5_POS                             (5U)
#define GPIO_POSR_POS5                                 (0x20U)
#define GPIO_POSR_POS6_POS                             (6U)
#define GPIO_POSR_POS6                                 (0x40U)
#define GPIO_POSR_POS7_POS                             (7U)
#define GPIO_POSR_POS7                                 (0x80U)

/*  Bit definition for GPIO_PORR register  */
#define GPIO_PORR_POR0_POS                             (0U)
#define GPIO_PORR_POR0                                 (0x01U)
#define GPIO_PORR_POR1_POS                             (1U)
#define GPIO_PORR_POR1                                 (0x02U)
#define GPIO_PORR_POR2_POS                             (2U)
#define GPIO_PORR_POR2                                 (0x04U)
#define GPIO_PORR_POR3_POS                             (3U)
#define GPIO_PORR_POR3                                 (0x08U)
#define GPIO_PORR_POR4_POS                             (4U)
#define GPIO_PORR_POR4                                 (0x10U)
#define GPIO_PORR_POR5_POS                             (5U)
#define GPIO_PORR_POR5                                 (0x20U)
#define GPIO_PORR_POR6_POS                             (6U)
#define GPIO_PORR_POR6                                 (0x40U)
#define GPIO_PORR_POR7_POS                             (7U)
#define GPIO_PORR_POR7                                 (0x80U)

/*  Bit definition for GPIO_POTR register  */
#define GPIO_POTR_POT0_POS                             (0U)
#define GPIO_POTR_POT0                                 (0x01U)
#define GPIO_POTR_POT1_POS                             (1U)
#define GPIO_POTR_POT1                                 (0x02U)
#define GPIO_POTR_POT2_POS                             (2U)
#define GPIO_POTR_POT2                                 (0x04U)
#define GPIO_POTR_POT3_POS                             (3U)
#define GPIO_POTR_POT3                                 (0x08U)
#define GPIO_POTR_POT4_POS                             (4U)
#define GPIO_POTR_POT4                                 (0x10U)
#define GPIO_POTR_POT5_POS                             (5U)
#define GPIO_POTR_POT5                                 (0x20U)
#define GPIO_POTR_POT6_POS                             (6U)
#define GPIO_POTR_POT6                                 (0x40U)
#define GPIO_POTR_POT7_POS                             (7U)
#define GPIO_POTR_POT7                                 (0x80U)

/*  Bit definition for GPIO_PCR register  */
#define GPIO_PCR_POUT_POS                              (0U)
#define GPIO_PCR_POUT                                  (0x0001U)
#define GPIO_PCR_POUTE_POS                             (1U)
#define GPIO_PCR_POUTE                                 (0x0002U)
#define GPIO_PCR_NOD_POS                               (2U)
#define GPIO_PCR_NOD                                   (0x0004U)
#define GPIO_PCR_DRV_POS                               (4U)
#define GPIO_PCR_DRV                                   (0x0010U)
#define GPIO_PCR_LTE_POS                               (5U)
#define GPIO_PCR_LTE                                   (0x0020U)
#define GPIO_PCR_PUU_POS                               (6U)
#define GPIO_PCR_PUU                                   (0x0040U)
#define GPIO_PCR_PIN_POS                               (8U)
#define GPIO_PCR_PIN                                   (0x0100U)
#define GPIO_PCR_INVE_POS                              (9U)
#define GPIO_PCR_INVE                                  (0x0200U)
#define GPIO_PCR_CINSEL_POS                            (10U)
#define GPIO_PCR_CINSEL                                (0x0400U)
#define GPIO_PCR_INTE_POS                              (11U)
#define GPIO_PCR_INTE                                  (0x0800U)
#define GPIO_PCR_FSEL_POS                              (12U)
#define GPIO_PCR_FSEL                                  (0x7000U)

/*  Bit definition for GPIO_PSPCR register  */
#define GPIO_PSPCR_SPFE                                (0x0003U)
#define GPIO_PSPCR_SPFE_0                              (0x0001U)
#define GPIO_PSPCR_SPFE_1                              (0x0002U)

/*  Bit definition for GPIO_PCCR register  */
#define GPIO_PCCR_RDWT_POS                             (14U)
#define GPIO_PCCR_RDWT                                 (0xC000U)
#define GPIO_PCCR_RDWT_0                               (0x4000U)
#define GPIO_PCCR_RDWT_1                               (0x8000U)

/*  Bit definition for GPIO_PINAER register  */
#define GPIO_PINAER_PINAE0_POS                         (0U)
#define GPIO_PINAER_PINAE0                             (0x0001U)
#define GPIO_PINAER_PINAE1_POS                         (1U)
#define GPIO_PINAER_PINAE1                             (0x0002U)
#define GPIO_PINAER_PINAE2_POS                         (2U)
#define GPIO_PINAER_PINAE2                             (0x0004U)
#define GPIO_PINAER_PINAE3_POS                         (3U)
#define GPIO_PINAER_PINAE3                             (0x0008U)
#define GPIO_PINAER_PINAE4_POS                         (4U)
#define GPIO_PINAER_PINAE4                             (0x0010U)
#define GPIO_PINAER_PINAE5_POS                         (5U)
#define GPIO_PINAER_PINAE5                             (0x0020U)
#define GPIO_PINAER_PINAE6_POS                         (6U)
#define GPIO_PINAER_PINAE6                             (0x0040U)
#define GPIO_PINAER_PINAE7_POS                         (7U)
#define GPIO_PINAER_PINAE7                             (0x0080U)
#define GPIO_PINAER_PINAE12_POS                        (12U)
#define GPIO_PINAER_PINAE12                            (0x1000U)
#define GPIO_PINAER_PINAE13_POS                        (13U)
#define GPIO_PINAER_PINAE13                            (0x2000U)
#define GPIO_PINAER_PINAE14_POS                        (14U)
#define GPIO_PINAER_PINAE14                            (0x4000U)

/*  Bit definition for GPIO_PWPR register  */
#define GPIO_PWPR_WE_POS                               (0U)
#define GPIO_PWPR_WE                                   (0x0001U)
#define GPIO_PWPR_WP_POS                               (8U)
#define GPIO_PWPR_WP                                   (0xFF00U)

/*******************************************************************************
                Bit definition for Peripheral I2C
*******************************************************************************/
/*  Bit definition for I2C_CR1 register  */
#define I2C_CR1_PE_POS                                 (0U)
#define I2C_CR1_PE                                     (0x00000001UL)
#define I2C_CR1_SMBUS_POS                              (1U)
#define I2C_CR1_SMBUS                                  (0x00000002UL)
#define I2C_CR1_SMBALRTEN_POS                          (2U)
#define I2C_CR1_SMBALRTEN                              (0x00000004UL)
#define I2C_CR1_SMBDEFAULTEN_POS                       (3U)
#define I2C_CR1_SMBDEFAULTEN                           (0x00000008UL)
#define I2C_CR1_SMBHOSTEN_POS                          (4U)
#define I2C_CR1_SMBHOSTEN                              (0x00000010UL)
#define I2C_CR1_FACKEN_POS                             (5U)
#define I2C_CR1_FACKEN                                 (0x00000020UL)
#define I2C_CR1_GCEN_POS                               (6U)
#define I2C_CR1_GCEN                                   (0x00000040UL)
#define I2C_CR1_RESTART_POS                            (7U)
#define I2C_CR1_RESTART                                (0x00000080UL)
#define I2C_CR1_START_POS                              (8U)
#define I2C_CR1_START                                  (0x00000100UL)
#define I2C_CR1_STOP_POS                               (9U)
#define I2C_CR1_STOP                                   (0x00000200UL)
#define I2C_CR1_ACK_POS                                (10U)
#define I2C_CR1_ACK                                    (0x00000400UL)
#define I2C_CR1_SWRST_POS                              (15U)
#define I2C_CR1_SWRST                                  (0x00008000UL)

/*  Bit definition for I2C_CR2 register  */
#define I2C_CR2_STARTIE_POS                            (0U)
#define I2C_CR2_STARTIE                                (0x00000001UL)
#define I2C_CR2_SLADDR0IE_POS                          (1U)
#define I2C_CR2_SLADDR0IE                              (0x00000002UL)
#define I2C_CR2_SLADDR1IE_POS                          (2U)
#define I2C_CR2_SLADDR1IE                              (0x00000004UL)
#define I2C_CR2_TENDIE_POS                             (3U)
#define I2C_CR2_TENDIE                                 (0x00000008UL)
#define I2C_CR2_STOPIE_POS                             (4U)
#define I2C_CR2_STOPIE                                 (0x00000010UL)
#define I2C_CR2_RFULLIE_POS                            (6U)
#define I2C_CR2_RFULLIE                                (0x00000040UL)
#define I2C_CR2_TEMPTYIE_POS                           (7U)
#define I2C_CR2_TEMPTYIE                               (0x00000080UL)
#define I2C_CR2_ARLOIE_POS                             (9U)
#define I2C_CR2_ARLOIE                                 (0x00000200UL)
#define I2C_CR2_NACKIE_POS                             (12U)
#define I2C_CR2_NACKIE                                 (0x00001000UL)
#define I2C_CR2_GENCALLIE_POS                          (20U)
#define I2C_CR2_GENCALLIE                              (0x00100000UL)
#define I2C_CR2_SMBDEFAULTIE_POS                       (21U)
#define I2C_CR2_SMBDEFAULTIE                           (0x00200000UL)
#define I2C_CR2_SMBHOSTIE_POS                          (22U)
#define I2C_CR2_SMBHOSTIE                              (0x00400000UL)
#define I2C_CR2_SMBALRTIE_POS                          (23U)
#define I2C_CR2_SMBALRTIE                              (0x00800000UL)

/*  Bit definition for I2C_SLR0 register  */
#define I2C_SLR0_SLADDR0_POS                           (0U)
#define I2C_SLR0_SLADDR0                               (0x000003FFUL)
#define I2C_SLR0_SLADDR0EN_POS                         (12U)
#define I2C_SLR0_SLADDR0EN                             (0x00001000UL)
#define I2C_SLR0_ADDRMOD0_POS                          (15U)
#define I2C_SLR0_ADDRMOD0                              (0x00008000UL)

/*  Bit definition for I2C_SLR1 register  */
#define I2C_SLR1_SLADDR1_POS                           (0U)
#define I2C_SLR1_SLADDR1                               (0x000003FFUL)
#define I2C_SLR1_SLADDR1EN_POS                         (12U)
#define I2C_SLR1_SLADDR1EN                             (0x00001000UL)
#define I2C_SLR1_ADDRMOD1_POS                          (15U)
#define I2C_SLR1_ADDRMOD1                              (0x00008000UL)

/*  Bit definition for I2C_SR register  */
#define I2C_SR_STARTF_POS                              (0U)
#define I2C_SR_STARTF                                  (0x00000001UL)
#define I2C_SR_SLADDR0F_POS                            (1U)
#define I2C_SR_SLADDR0F                                (0x00000002UL)
#define I2C_SR_SLADDR1F_POS                            (2U)
#define I2C_SR_SLADDR1F                                (0x00000004UL)
#define I2C_SR_TENDF_POS                               (3U)
#define I2C_SR_TENDF                                   (0x00000008UL)
#define I2C_SR_STOPF_POS                               (4U)
#define I2C_SR_STOPF                                   (0x00000010UL)
#define I2C_SR_RFULLF_POS                              (6U)
#define I2C_SR_RFULLF                                  (0x00000040UL)
#define I2C_SR_TEMPTYF_POS                             (7U)
#define I2C_SR_TEMPTYF                                 (0x00000080UL)
#define I2C_SR_ARLOF_POS                               (9U)
#define I2C_SR_ARLOF                                   (0x00000200UL)
#define I2C_SR_ACKRF_POS                               (10U)
#define I2C_SR_ACKRF                                   (0x00000400UL)
#define I2C_SR_NACKF_POS                               (12U)
#define I2C_SR_NACKF                                   (0x00001000UL)
#define I2C_SR_MSL_POS                                 (16U)
#define I2C_SR_MSL                                     (0x00010000UL)
#define I2C_SR_BUSY_POS                                (17U)
#define I2C_SR_BUSY                                    (0x00020000UL)
#define I2C_SR_TRA_POS                                 (18U)
#define I2C_SR_TRA                                     (0x00040000UL)
#define I2C_SR_GENCALLF_POS                            (20U)
#define I2C_SR_GENCALLF                                (0x00100000UL)
#define I2C_SR_SMBDEFAULTF_POS                         (21U)
#define I2C_SR_SMBDEFAULTF                             (0x00200000UL)
#define I2C_SR_SMBHOSTF_POS                            (22U)
#define I2C_SR_SMBHOSTF                                (0x00400000UL)
#define I2C_SR_SMBALRTF_POS                            (23U)
#define I2C_SR_SMBALRTF                                (0x00800000UL)

/*  Bit definition for I2C_CLR register  */
#define I2C_CLR_STARTFCLR_POS                          (0U)
#define I2C_CLR_STARTFCLR                              (0x00000001UL)
#define I2C_CLR_SLADDR0FCLR_POS                        (1U)
#define I2C_CLR_SLADDR0FCLR                            (0x00000002UL)
#define I2C_CLR_SLADDR1FCLR_POS                        (2U)
#define I2C_CLR_SLADDR1FCLR                            (0x00000004UL)
#define I2C_CLR_TENDFCLR_POS                           (3U)
#define I2C_CLR_TENDFCLR                               (0x00000008UL)
#define I2C_CLR_STOPFCLR_POS                           (4U)
#define I2C_CLR_STOPFCLR                               (0x00000010UL)
#define I2C_CLR_RFULLFCLR_POS                          (6U)
#define I2C_CLR_RFULLFCLR                              (0x00000040UL)
#define I2C_CLR_TEMPTYFCLR_POS                         (7U)
#define I2C_CLR_TEMPTYFCLR                             (0x00000080UL)
#define I2C_CLR_ARLOFCLR_POS                           (9U)
#define I2C_CLR_ARLOFCLR                               (0x00000200UL)
#define I2C_CLR_NACKFCLR_POS                           (12U)
#define I2C_CLR_NACKFCLR                               (0x00001000UL)
#define I2C_CLR_GENCALLFCLR_POS                        (20U)
#define I2C_CLR_GENCALLFCLR                            (0x00100000UL)
#define I2C_CLR_SMBDEFAULTFCLR_POS                     (21U)
#define I2C_CLR_SMBDEFAULTFCLR                         (0x00200000UL)
#define I2C_CLR_SMBHOSTFCLR_POS                        (22U)
#define I2C_CLR_SMBHOSTFCLR                            (0x00400000UL)
#define I2C_CLR_SMBALRTFCLR_POS                        (23U)
#define I2C_CLR_SMBALRTFCLR                            (0x00800000UL)

/*  Bit definition for I2C_DTR register  */
#define I2C_DTR_DT                                     (0xFFU)

/*  Bit definition for I2C_DRR register  */
#define I2C_DRR_DR                                     (0xFFU)

/*  Bit definition for I2C_CCR register  */
#define I2C_CCR_SLOWW_POS                              (0U)
#define I2C_CCR_SLOWW                                  (0x0000001FUL)
#define I2C_CCR_SHIGHW_POS                             (8U)
#define I2C_CCR_SHIGHW                                 (0x00001F00UL)
#define I2C_CCR_CKDIV_POS                              (16U)
#define I2C_CCR_CKDIV                                  (0x00070000UL)
#define I2C_CCR_CKDIV_0                                (0x00010000UL)
#define I2C_CCR_CKDIV_1                                (0x00020000UL)
#define I2C_CCR_CKDIV_2                                (0x00040000UL)

/*  Bit definition for I2C_FLTR register  */
#define I2C_FLTR_DNF_POS                               (0U)
#define I2C_FLTR_DNF                                   (0x00000003UL)
#define I2C_FLTR_DNF_0                                 (0x00000001UL)
#define I2C_FLTR_DNF_1                                 (0x00000002UL)
#define I2C_FLTR_DNFEN_POS                             (4U)
#define I2C_FLTR_DNFEN                                 (0x00000010UL)

/*******************************************************************************
                Bit definition for Peripheral ICG
*******************************************************************************/
/*  Bit definition for ICG_ICG0 register  */
#define ICG_ICG0_SWDTAUTS_POS                          (0U)
#define ICG_ICG0_SWDTAUTS                              (0x00000001UL)
#define ICG_ICG0_SWDTITS_POS                           (1U)
#define ICG_ICG0_SWDTITS                               (0x00000002UL)
#define ICG_ICG0_SWDTPERI_POS                          (2U)
#define ICG_ICG0_SWDTPERI                              (0x0000000CUL)
#define ICG_ICG0_SWDTPERI_0                            (0x00000004UL)
#define ICG_ICG0_SWDTPERI_1                            (0x00000008UL)
#define ICG_ICG0_SWDTCKS_POS                           (4U)
#define ICG_ICG0_SWDTCKS                               (0x000000F0UL)
#define ICG_ICG0_SWDTWDPT_POS                          (8U)
#define ICG_ICG0_SWDTWDPT                              (0x00000F00UL)
#define ICG_ICG0_SWDTSLPOFF_POS                        (12U)
#define ICG_ICG0_SWDTSLPOFF                            (0x00001000UL)
#define ICG_ICG0_HRCREQS_POS                           (16U)
#define ICG_ICG0_HRCREQS                               (0x000F0000UL)

/*  Bit definition for ICG_ICG1 register  */
#define ICG_ICG1_DFS_POS                               (0U)
#define ICG_ICG1_DFS                                   (0x00000003UL)
#define ICG_ICG1_DFS_0                                 (0x00000001UL)
#define ICG_ICG1_DFS_1                                 (0x00000002UL)
#define ICG_ICG1_DFDIS_POS                             (2U)
#define ICG_ICG1_DFDIS                                 (0x00000004UL)
#define ICG_ICG1_LVDLVL_POS                            (8U)
#define ICG_ICG1_LVDLVL                                (0x00000F00UL)
#define ICG_ICG1_NMIS_POS                              (12U)
#define ICG_ICG1_NMIS                                  (0x00001000UL)
#define ICG_ICG1_IRS_POS                               (13U)
#define ICG_ICG1_IRS                                   (0x00002000UL)
#define ICG_ICG1_IRDIS_POS                             (14U)
#define ICG_ICG1_IRDIS                                 (0x00004000UL)
#define ICG_ICG1_LVDDIS_POS                            (15U)
#define ICG_ICG1_LVDDIS                                (0x00008000UL)
#define ICG_ICG1_LKUPDIS_POS                           (16U)
#define ICG_ICG1_LKUPDIS                               (0x00010000UL)

/*  Bit definition for ICG_ICG2 register  */
#define ICG_ICG2                                       (0xFFFFFFFFUL)

/*  Bit definition for ICG_ICG3 register  */
#define ICG_ICG3                                       (0xFFFFFFFFUL)

/*  Bit definition for ICG_ICG4 register  */
#define ICG_ICG4                                       (0xFFFFFFFFUL)

/*  Bit definition for ICG_ICG5 register  */
#define ICG_ICG5                                       (0xFFFFFFFFUL)

/*  Bit definition for ICG_ICG6 register  */
#define ICG_ICG6                                       (0xFFFFFFFFUL)

/*******************************************************************************
                Bit definition for Peripheral INTC
*******************************************************************************/
/*  Bit definition for INTC_NMIER register  */
#define INTC_NMIER_XTALSTPEN_POS                       (1U)
#define INTC_NMIER_XTALSTPEN                           (0x00000002UL)
#define INTC_NMIER_SWDTEN_POS                          (2U)
#define INTC_NMIER_SWDTEN                              (0x00000004UL)
#define INTC_NMIER_PVDEN_POS                           (3U)
#define INTC_NMIER_PVDEN                               (0x00000008UL)

/*  Bit definition for INTC_NMIFR register  */
#define INTC_NMIFR_XTALSTPF_POS                        (1U)
#define INTC_NMIFR_XTALSTPF                            (0x00000002UL)
#define INTC_NMIFR_SWDTF_POS                           (2U)
#define INTC_NMIFR_SWDTF                               (0x00000004UL)
#define INTC_NMIFR_PVDF_POS                            (3U)
#define INTC_NMIFR_PVDF                                (0x00000008UL)

/*  Bit definition for INTC_NMICLR register  */
#define INTC_NMICLR_XTALSTPCL_POS                      (1U)
#define INTC_NMICLR_XTALSTPCL                          (0x00000002UL)
#define INTC_NMICLR_SWDTCL_POS                         (2U)
#define INTC_NMICLR_SWDTCL                             (0x00000004UL)
#define INTC_NMICLR_PVDCL_POS                          (3U)
#define INTC_NMICLR_PVDCL                              (0x00000008UL)

/*  Bit definition for INTC_EVTER register  */
#define INTC_EVTER_EVTEN0_POS                          (0U)
#define INTC_EVTER_EVTEN0                              (0x00000001UL)
#define INTC_EVTER_EVTEN1_POS                          (1U)
#define INTC_EVTER_EVTEN1                              (0x00000002UL)
#define INTC_EVTER_EVTEN2_POS                          (2U)
#define INTC_EVTER_EVTEN2                              (0x00000004UL)
#define INTC_EVTER_EVTEN3_POS                          (3U)
#define INTC_EVTER_EVTEN3                              (0x00000008UL)
#define INTC_EVTER_EVTEN4_POS                          (4U)
#define INTC_EVTER_EVTEN4                              (0x00000010UL)
#define INTC_EVTER_EVTEN5_POS                          (5U)
#define INTC_EVTER_EVTEN5                              (0x00000020UL)
#define INTC_EVTER_EVTEN6_POS                          (6U)
#define INTC_EVTER_EVTEN6                              (0x00000040UL)
#define INTC_EVTER_EVTEN7_POS                          (7U)
#define INTC_EVTER_EVTEN7                              (0x00000080UL)

/*  Bit definition for INTC_EKEYCR register  */
#define INTC_EKEYCR_EKEY0EN_POS                        (0U)
#define INTC_EKEYCR_EKEY0EN                            (0x00000001UL)
#define INTC_EKEYCR_EKEY1EN_POS                        (1U)
#define INTC_EKEYCR_EKEY1EN                            (0x00000002UL)
#define INTC_EKEYCR_EKEY2EN_POS                        (2U)
#define INTC_EKEYCR_EKEY2EN                            (0x00000004UL)
#define INTC_EKEYCR_EKEY3EN_POS                        (3U)
#define INTC_EKEYCR_EKEY3EN                            (0x00000008UL)
#define INTC_EKEYCR_EKEY4EN_POS                        (4U)
#define INTC_EKEYCR_EKEY4EN                            (0x00000010UL)
#define INTC_EKEYCR_EKEY5EN_POS                        (5U)
#define INTC_EKEYCR_EKEY5EN                            (0x00000020UL)
#define INTC_EKEYCR_EKEY6EN_POS                        (6U)
#define INTC_EKEYCR_EKEY6EN                            (0x00000040UL)
#define INTC_EKEYCR_EKEY7EN_POS                        (7U)
#define INTC_EKEYCR_EKEY7EN                            (0x00000080UL)

/*  Bit definition for INTC_FPRCR register  */
#define INTC_FPRCR_FPRC                                (0x000000FFUL)
#define INTC_FPRCR_FPRC_0                              (0x00000001UL)
#define INTC_FPRCR_FPRC_1                              (0x00000002UL)
#define INTC_FPRCR_FPRC_2                              (0x00000004UL)
#define INTC_FPRCR_FPRC_3                              (0x00000008UL)
#define INTC_FPRCR_FPRC_4                              (0x00000010UL)
#define INTC_FPRCR_FPRC_5                              (0x00000020UL)
#define INTC_FPRCR_FPRC_6                              (0x00000040UL)
#define INTC_FPRCR_FPRC_7                              (0x00000080UL)

/*  Bit definition for INTC_EIRQCR register  */
#define INTC_EIRQCR_EIRQTRG_POS                        (0U)
#define INTC_EIRQCR_EIRQTRG                            (0x00000003UL)
#define INTC_EIRQCR_EIRQTRG_0                          (0x00000001UL)
#define INTC_EIRQCR_EIRQTRG_1                          (0x00000002UL)
#define INTC_EIRQCR_EIRQFCLK_POS                       (4U)
#define INTC_EIRQCR_EIRQFCLK                           (0x00000030UL)
#define INTC_EIRQCR_EIRQFCLK_0                         (0x00000010UL)
#define INTC_EIRQCR_EIRQFCLK_1                         (0x00000020UL)
#define INTC_EIRQCR_EIRQFEN_POS                        (7U)
#define INTC_EIRQCR_EIRQFEN                            (0x00000080UL)

/*  Bit definition for INTC_WUPENR register  */
#define INTC_WUPENR_EIRQWUEN_POS                       (0U)
#define INTC_WUPENR_EIRQWUEN                           (0x00000FFFUL)
#define INTC_WUPENR_EIRQWUEN_0                         (0x00000001UL)
#define INTC_WUPENR_EIRQWUEN_1                         (0x00000002UL)
#define INTC_WUPENR_EIRQWUEN_2                         (0x00000004UL)
#define INTC_WUPENR_EIRQWUEN_3                         (0x00000008UL)
#define INTC_WUPENR_EIRQWUEN_4                         (0x00000010UL)
#define INTC_WUPENR_EIRQWUEN_5                         (0x00000020UL)
#define INTC_WUPENR_EIRQWUEN_6                         (0x00000040UL)
#define INTC_WUPENR_EIRQWUEN_7                         (0x00000080UL)
#define INTC_WUPENR_EIRQWUEN_8                         (0x00000100UL)
#define INTC_WUPENR_EIRQWUEN_9                         (0x00000200UL)
#define INTC_WUPENR_EIRQWUEN_10                        (0x00000400UL)
#define INTC_WUPENR_EIRQWUEN_11                        (0x00000800UL)
#define INTC_WUPENR_SWDTWUEN_POS                       (16U)
#define INTC_WUPENR_SWDTWUEN                           (0x00010000UL)
#define INTC_WUPENR_EKEYWUEN_POS                       (17U)
#define INTC_WUPENR_EKEYWUEN                           (0x00020000UL)
#define INTC_WUPENR_TMR0CMPWUEN_POS                    (18U)
#define INTC_WUPENR_TMR0CMPWUEN                        (0x00040000UL)
#define INTC_WUPENR_PVDWUEN_POS                        (22U)
#define INTC_WUPENR_PVDWUEN                            (0x00400000UL)
#define INTC_WUPENR_RTCALMWUEN_POS                     (23U)
#define INTC_WUPENR_RTCALMWUEN                         (0x00800000UL)
#define INTC_WUPENR_RTCPRDWUEN_POS                     (24U)
#define INTC_WUPENR_RTCPRDWUEN                         (0x01000000UL)

/*  Bit definition for INTC_EIRQFR register  */
#define INTC_EIRQFR_EIRQF                              (0x00000FFFUL)
#define INTC_EIRQFR_EIRQF_0                            (0x00000001UL)
#define INTC_EIRQFR_EIRQF_1                            (0x00000002UL)
#define INTC_EIRQFR_EIRQF_2                            (0x00000004UL)
#define INTC_EIRQFR_EIRQF_3                            (0x00000008UL)
#define INTC_EIRQFR_EIRQF_4                            (0x00000010UL)
#define INTC_EIRQFR_EIRQF_5                            (0x00000020UL)
#define INTC_EIRQFR_EIRQF_6                            (0x00000040UL)
#define INTC_EIRQFR_EIRQF_7                            (0x00000080UL)
#define INTC_EIRQFR_EIRQF_8                            (0x00000100UL)
#define INTC_EIRQFR_EIRQF_9                            (0x00000200UL)
#define INTC_EIRQFR_EIRQF_10                           (0x00000400UL)
#define INTC_EIRQFR_EIRQF_11                           (0x00000800UL)

/*  Bit definition for INTC_EIRQCLR register  */
#define INTC_EIRQCLR_EIRQCL                            (0x00000FFFUL)
#define INTC_EIRQCLR_EIRQCL_0                          (0x00000001UL)
#define INTC_EIRQCLR_EIRQCL_1                          (0x00000002UL)
#define INTC_EIRQCLR_EIRQCL_2                          (0x00000004UL)
#define INTC_EIRQCLR_EIRQCL_3                          (0x00000008UL)
#define INTC_EIRQCLR_EIRQCL_4                          (0x00000010UL)
#define INTC_EIRQCLR_EIRQCL_5                          (0x00000020UL)
#define INTC_EIRQCLR_EIRQCL_6                          (0x00000040UL)
#define INTC_EIRQCLR_EIRQCL_7                          (0x00000080UL)
#define INTC_EIRQCLR_EIRQCL_8                          (0x00000100UL)
#define INTC_EIRQCLR_EIRQCL_9                          (0x00000200UL)
#define INTC_EIRQCLR_EIRQCL_10                         (0x00000400UL)
#define INTC_EIRQCLR_EIRQCL_11                         (0x00000800UL)

/*  Bit definition for INTC_ISELAR register  */
#define INTC_ISELAR_ISEL                               (0x0000000FUL)

/*  Bit definition for INTC_ISELBR register  */
#define INTC_ISELBR_ISEL1_POS                          (1U)
#define INTC_ISELBR_ISEL1                              (0x00000002UL)
#define INTC_ISELBR_ISEL2_POS                          (2U)
#define INTC_ISELBR_ISEL2                              (0x00000004UL)
#define INTC_ISELBR_ISEL3_POS                          (3U)
#define INTC_ISELBR_ISEL3                              (0x00000008UL)
#define INTC_ISELBR_ISEL4_POS                          (4U)
#define INTC_ISELBR_ISEL4                              (0x00000010UL)
#define INTC_ISELBR_ISEL5_POS                          (5U)
#define INTC_ISELBR_ISEL5                              (0x00000020UL)
#define INTC_ISELBR_ISEL6_POS                          (6U)
#define INTC_ISELBR_ISEL6                              (0x00000040UL)
#define INTC_ISELBR_ISEL7_POS                          (7U)
#define INTC_ISELBR_ISEL7                              (0x00000080UL)
#define INTC_ISELBR_ISEL8_POS                          (8U)
#define INTC_ISELBR_ISEL8                              (0x00000100UL)
#define INTC_ISELBR_ISEL9_POS                          (9U)
#define INTC_ISELBR_ISEL9                              (0x00000200UL)
#define INTC_ISELBR_ISEL10_POS                         (10U)
#define INTC_ISELBR_ISEL10                             (0x00000400UL)
#define INTC_ISELBR_ISEL11_POS                         (11U)
#define INTC_ISELBR_ISEL11                             (0x00000800UL)
#define INTC_ISELBR_ISEL12_POS                         (12U)
#define INTC_ISELBR_ISEL12                             (0x00001000UL)
#define INTC_ISELBR_ISEL13_POS                         (13U)
#define INTC_ISELBR_ISEL13                             (0x00002000UL)
#define INTC_ISELBR_ISEL14_POS                         (14U)
#define INTC_ISELBR_ISEL14                             (0x00004000UL)
#define INTC_ISELBR_ISEL15_POS                         (15U)
#define INTC_ISELBR_ISEL15                             (0x00008000UL)

/*******************************************************************************
                Bit definition for Peripheral PWC
*******************************************************************************/
/*  Bit definition for PWC_STPMCR register  */
#define PWC_STPMCR_FLNWT_POS                           (0U)
#define PWC_STPMCR_FLNWT                               (0x01U)
#define PWC_STPMCR_CKSHRC_POS                          (1U)
#define PWC_STPMCR_CKSHRC                              (0x02U)
#define PWC_STPMCR_HAPORDIS_POS                        (3U)
#define PWC_STPMCR_HAPORDIS                            (0x08U)
#define PWC_STPMCR_STOP_POS                            (7U)
#define PWC_STPMCR_STOP                                (0x80U)

/*  Bit definition for PWC_PWRC register  */
#define PWC_PWRC_PWDRV_POS                             (0U)
#define PWC_PWRC_PWDRV                                 (0x07U)
#define PWC_PWRC_PWDRV_0                               (0x01U)
#define PWC_PWRC_PWDRV_1                               (0x02U)
#define PWC_PWRC_PWDRV_2                               (0x04U)
#define PWC_PWRC_DVS_POS                               (3U)
#define PWC_PWRC_DVS                                   (0x08U)
#define PWC_PWRC_VHRCE_POS                             (6U)
#define PWC_PWRC_VHRCE                                 (0x40U)
#define PWC_PWRC_HRCPWRDY_POS                          (7U)
#define PWC_PWRC_HRCPWRDY                              (0x80U)

/*  Bit definition for PWC_PWRMON register  */
#define PWC_PWRMON_PWMONSEL_POS                        (0U)
#define PWC_PWRMON_PWMONSEL                            (0x01U)
#define PWC_PWRMON_PWMONE_POS                          (1U)
#define PWC_PWRMON_PWMONE                              (0x02U)

/*  Bit definition for PWC_RAMCR register  */
#define PWC_RAMCR_RPRTA_POS                            (0U)
#define PWC_RAMCR_RPRTA                                (0x03U)
#define PWC_RAMCR_RPRTA_0                              (0x01U)
#define PWC_RAMCR_RPRTA_1                              (0x02U)
#define PWC_RAMCR_RPERDIS_POS                          (4U)
#define PWC_RAMCR_RPERDIS                              (0x10U)
#define PWC_RAMCR_RPERF_POS                            (5U)
#define PWC_RAMCR_RPERF                                (0x20U)

/*  Bit definition for PWC_LVDCSR register  */
#define PWC_LVDCSR_EXVCCINEN_POS                       (0U)
#define PWC_LVDCSR_EXVCCINEN                           (0x01U)
#define PWC_LVDCSR_LVIF_POS                            (3U)
#define PWC_LVDCSR_LVIF                                (0x08U)
#define PWC_LVDCSR_DETF_POS                            (4U)
#define PWC_LVDCSR_DETF                                (0x10U)
#define PWC_LVDCSR_CMPOE_POS                           (7U)
#define PWC_LVDCSR_CMPOE                               (0x80U)

/*  Bit definition for PWC_FPRC register  */
#define PWC_FPRC_CKRWE_POS                             (0U)
#define PWC_FPRC_CKRWE                                 (0x0001U)
#define PWC_FPRC_PWRWE_POS                             (1U)
#define PWC_FPRC_PWRWE                                 (0x0002U)
#define PWC_FPRC_FPRCB2_POS                            (2U)
#define PWC_FPRC_FPRCB2                                (0x0004U)
#define PWC_FPRC_LVRWE_POS                             (3U)
#define PWC_FPRC_LVRWE                                 (0x0008U)
#define PWC_FPRC_FPRCB4_POS                            (4U)
#define PWC_FPRC_FPRCB4                                (0x0010U)
#define PWC_FPRC_FPRCB5_POS                            (5U)
#define PWC_FPRC_FPRCB5                                (0x0020U)
#define PWC_FPRC_FPRCB6_POS                            (6U)
#define PWC_FPRC_FPRCB6                                (0x0040U)
#define PWC_FPRC_FPRCB7_POS                            (7U)
#define PWC_FPRC_FPRCB7                                (0x0080U)
#define PWC_FPRC_FPRCWE_POS                            (8U)
#define PWC_FPRC_FPRCWE                                (0xFF00U)
#define PWC_FPRC_FPRCWE_0                              (0x0100U)
#define PWC_FPRC_FPRCWE_1                              (0x0200U)
#define PWC_FPRC_FPRCWE_2                              (0x0400U)
#define PWC_FPRC_FPRCWE_3                              (0x0800U)
#define PWC_FPRC_FPRCWE_4                              (0x1000U)
#define PWC_FPRC_FPRCWE_5                              (0x2000U)
#define PWC_FPRC_FPRCWE_6                              (0x4000U)
#define PWC_FPRC_FPRCWE_7                              (0x8000U)

/*  Bit definition for PWC_DBGC register  */
#define PWC_DBGC_DBGEN_POS                             (0U)
#define PWC_DBGC_DBGEN                                 (0x01U)
#define PWC_DBGC_DBGWKF_POS                            (1U)
#define PWC_DBGC_DBGWKF                                (0x02U)

/*******************************************************************************
                Bit definition for Peripheral RMU
*******************************************************************************/
/*  Bit definition for RMU_RSTF0 register  */
#define RMU_RSTF0_PORF_POS                             (0U)
#define RMU_RSTF0_PORF                                 (0x0001U)
#define RMU_RSTF0_PINRF_POS                            (1U)
#define RMU_RSTF0_PINRF                                (0x0002U)
#define RMU_RSTF0_LVRF_POS                             (2U)
#define RMU_RSTF0_LVRF                                 (0x0004U)
#define RMU_RSTF0_WDRF_POS                             (5U)
#define RMU_RSTF0_WDRF                                 (0x0020U)
#define RMU_RSTF0_SWRF_POS                             (8U)
#define RMU_RSTF0_SWRF                                 (0x0100U)
#define RMU_RSTF0_RAMPERF_POS                          (10U)
#define RMU_RSTF0_RAMPERF                              (0x0400U)
#define RMU_RSTF0_CPULKUPRF_POS                        (12U)
#define RMU_RSTF0_CPULKUPRF                            (0x1000U)
#define RMU_RSTF0_XTALERF_POS                          (13U)
#define RMU_RSTF0_XTALERF                              (0x2000U)
#define RMU_RSTF0_MULTIRF_POS                          (14U)
#define RMU_RSTF0_MULTIRF                              (0x4000U)
#define RMU_RSTF0_CLRF_POS                             (15U)
#define RMU_RSTF0_CLRF                                 (0x8000U)

/*******************************************************************************
                Bit definition for Peripheral RTC
*******************************************************************************/
/*  Bit definition for RTC_CR0 register  */
#define RTC_CR0_RESET                                  (0x01U)

/*  Bit definition for RTC_CR1 register  */
#define RTC_CR1_PRDS_POS                               (0U)
#define RTC_CR1_PRDS                                   (0x07U)
#define RTC_CR1_AMPM_POS                               (3U)
#define RTC_CR1_AMPM                                   (0x08U)
#define RTC_CR1_ONEHZOE_POS                            (5U)
#define RTC_CR1_ONEHZOE                                (0x20U)
#define RTC_CR1_START_POS                              (7U)
#define RTC_CR1_START                                  (0x80U)

/*  Bit definition for RTC_CR2 register  */
#define RTC_CR2_RWREQ_POS                              (0U)
#define RTC_CR2_RWREQ                                  (0x01U)
#define RTC_CR2_RWEN_POS                               (1U)
#define RTC_CR2_RWEN                                   (0x02U)
#define RTC_CR2_PRDF_POS                               (2U)
#define RTC_CR2_PRDF                                   (0x04U)
#define RTC_CR2_ALMF_POS                               (3U)
#define RTC_CR2_ALMF                                   (0x08U)
#define RTC_CR2_PRDIE_POS                              (5U)
#define RTC_CR2_PRDIE                                  (0x20U)
#define RTC_CR2_ALMIE_POS                              (6U)
#define RTC_CR2_ALMIE                                  (0x40U)
#define RTC_CR2_ALME_POS                               (7U)
#define RTC_CR2_ALME                                   (0x80U)

/*  Bit definition for RTC_CR3 register  */
#define RTC_CR3_LRCEN_POS                              (4U)
#define RTC_CR3_LRCEN                                  (0x10U)
#define RTC_CR3_RCKSEL_POS                             (7U)
#define RTC_CR3_RCKSEL                                 (0x80U)

/*  Bit definition for RTC_SEC register  */
#define RTC_SEC_SECU_POS                               (0U)
#define RTC_SEC_SECU                                   (0x0FU)
#define RTC_SEC_SECD_POS                               (4U)
#define RTC_SEC_SECD                                   (0x70U)

/*  Bit definition for RTC_MIN register  */
#define RTC_MIN_MINU_POS                               (0U)
#define RTC_MIN_MINU                                   (0x0FU)
#define RTC_MIN_MIND_POS                               (4U)
#define RTC_MIN_MIND                                   (0x70U)

/*  Bit definition for RTC_HOUR register  */
#define RTC_HOUR_HOURU_POS                             (0U)
#define RTC_HOUR_HOURU                                 (0x0FU)
#define RTC_HOUR_HOURD_POS                             (4U)
#define RTC_HOUR_HOURD                                 (0x30U)
#define RTC_HOUR_HOURD_0                               (0x10U)
#define RTC_HOUR_HOURD_1                               (0x20U)

/*  Bit definition for RTC_WEEK register  */
#define RTC_WEEK_WEEK                                  (0x07U)

/*  Bit definition for RTC_DAY register  */
#define RTC_DAY_DAYU_POS                               (0U)
#define RTC_DAY_DAYU                                   (0x0FU)
#define RTC_DAY_DAYD_POS                               (4U)
#define RTC_DAY_DAYD                                   (0x30U)

/*  Bit definition for RTC_MON register  */
#define RTC_MON_MON                                    (0x1FU)

/*  Bit definition for RTC_YEAR register  */
#define RTC_YEAR_YEARU_POS                             (0U)
#define RTC_YEAR_YEARU                                 (0x0FU)
#define RTC_YEAR_YEARD_POS                             (4U)
#define RTC_YEAR_YEARD                                 (0xF0U)

/*  Bit definition for RTC_ALMMIN register  */
#define RTC_ALMMIN_ALMMINU_POS                         (0U)
#define RTC_ALMMIN_ALMMINU                             (0x0FU)
#define RTC_ALMMIN_ALMMIND_POS                         (4U)
#define RTC_ALMMIN_ALMMIND                             (0x70U)

/*  Bit definition for RTC_ALMHOUR register  */
#define RTC_ALMHOUR_ALMHOURU_POS                       (0U)
#define RTC_ALMHOUR_ALMHOURU                           (0x0FU)
#define RTC_ALMHOUR_ALMHOURD_POS                       (4U)
#define RTC_ALMHOUR_ALMHOURD                           (0x30U)
#define RTC_ALMHOUR_ALMHOURD_0                         (0x10U)
#define RTC_ALMHOUR_ALMHOURD_1                         (0x20U)

/*  Bit definition for RTC_ALMWEEK register  */
#define RTC_ALMWEEK_ALMWEEK                            (0x7FU)
#define RTC_ALMWEEK_ALMWEEK_0                          (0x01U)
#define RTC_ALMWEEK_ALMWEEK_1                          (0x02U)
#define RTC_ALMWEEK_ALMWEEK_2                          (0x04U)
#define RTC_ALMWEEK_ALMWEEK_3                          (0x08U)
#define RTC_ALMWEEK_ALMWEEK_4                          (0x10U)
#define RTC_ALMWEEK_ALMWEEK_5                          (0x20U)
#define RTC_ALMWEEK_ALMWEEK_6                          (0x40U)

/*  Bit definition for RTC_ERRCRH register  */
#define RTC_ERRCRH_COMP8_POS                           (0U)
#define RTC_ERRCRH_COMP8                               (0x01U)
#define RTC_ERRCRH_COMPEN_POS                          (7U)
#define RTC_ERRCRH_COMPEN                              (0x80U)

/*  Bit definition for RTC_ERRCRL register  */
#define RTC_ERRCRL_COMP                                (0xFFU)

/*******************************************************************************
                Bit definition for Peripheral SPI
*******************************************************************************/
/*  Bit definition for SPI_DR register  */
#define SPI_DR_SPD                                     (0x0000FFFFUL)

/*  Bit definition for SPI_CR1 register  */
#define SPI_CR1_SPIMDS_POS                             (0U)
#define SPI_CR1_SPIMDS                                 (0x00000001UL)
#define SPI_CR1_TXMDS_POS                              (1U)
#define SPI_CR1_TXMDS                                  (0x00000002UL)
#define SPI_CR1_MSTR_POS                               (3U)
#define SPI_CR1_MSTR                                   (0x00000008UL)
#define SPI_CR1_SPLPBK_POS                             (4U)
#define SPI_CR1_SPLPBK                                 (0x00000010UL)
#define SPI_CR1_SPLPBK2_POS                            (5U)
#define SPI_CR1_SPLPBK2                                (0x00000020UL)
#define SPI_CR1_SPE_POS                                (6U)
#define SPI_CR1_SPE                                    (0x00000040UL)
#define SPI_CR1_EIE_POS                                (8U)
#define SPI_CR1_EIE                                    (0x00000100UL)
#define SPI_CR1_TXIE_POS                               (9U)
#define SPI_CR1_TXIE                                   (0x00000200UL)
#define SPI_CR1_RXIE_POS                               (10U)
#define SPI_CR1_RXIE                                   (0x00000400UL)
#define SPI_CR1_IDIE_POS                               (11U)
#define SPI_CR1_IDIE                                   (0x00000800UL)
#define SPI_CR1_MODFE_POS                              (12U)
#define SPI_CR1_MODFE                                  (0x00001000UL)
#define SPI_CR1_PATE_POS                               (13U)
#define SPI_CR1_PATE                                   (0x00002000UL)
#define SPI_CR1_PAOE_POS                               (14U)
#define SPI_CR1_PAOE                                   (0x00004000UL)
#define SPI_CR1_PAE_POS                                (15U)
#define SPI_CR1_PAE                                    (0x00008000UL)

/*  Bit definition for SPI_CFG1 register  */
#define SPI_CFG1_SS0PV_POS                             (8U)
#define SPI_CFG1_SS0PV                                 (0x00000100UL)

/*  Bit definition for SPI_SR register  */
#define SPI_SR_OVRERF_POS                              (0U)
#define SPI_SR_OVRERF                                  (0x00000001UL)
#define SPI_SR_IDLNF_POS                               (1U)
#define SPI_SR_IDLNF                                   (0x00000002UL)
#define SPI_SR_MODFERF_POS                             (2U)
#define SPI_SR_MODFERF                                 (0x00000004UL)
#define SPI_SR_PERF_POS                                (3U)
#define SPI_SR_PERF                                    (0x00000008UL)
#define SPI_SR_UDRERF_POS                              (4U)
#define SPI_SR_UDRERF                                  (0x00000010UL)
#define SPI_SR_TDEF_POS                                (5U)
#define SPI_SR_TDEF                                    (0x00000020UL)
#define SPI_SR_RDFF_POS                                (7U)
#define SPI_SR_RDFF                                    (0x00000080UL)

/*  Bit definition for SPI_CFG2 register  */
#define SPI_CFG2_CPHA_POS                              (0U)
#define SPI_CFG2_CPHA                                  (0x00000001UL)
#define SPI_CFG2_CPOL_POS                              (1U)
#define SPI_CFG2_CPOL                                  (0x00000002UL)
#define SPI_CFG2_MBR_POS                               (2U)
#define SPI_CFG2_MBR                                   (0x0000001CUL)
#define SPI_CFG2_MBR_0                                 (0x00000004UL)
#define SPI_CFG2_MBR_1                                 (0x00000008UL)
#define SPI_CFG2_MBR_2                                 (0x00000010UL)
#define SPI_CFG2_DSIZE_POS                             (8U)
#define SPI_CFG2_DSIZE                                 (0x00000100UL)
#define SPI_CFG2_LSBF_POS                              (12U)
#define SPI_CFG2_LSBF                                  (0x00001000UL)

/*******************************************************************************
                Bit definition for Peripheral SWDT
*******************************************************************************/
/*  Bit definition for SWDT_CR register  */
#define SWDT_CR_PERI_POS                               (0U)
#define SWDT_CR_PERI                                   (0x00000003UL)
#define SWDT_CR_PERI_0                                 (0x00000001UL)
#define SWDT_CR_PERI_1                                 (0x00000002UL)
#define SWDT_CR_CKS_POS                                (4U)
#define SWDT_CR_CKS                                    (0x000000F0UL)
#define SWDT_CR_CKS_0                                  (0x00000010UL)
#define SWDT_CR_CKS_1                                  (0x00000020UL)
#define SWDT_CR_CKS_2                                  (0x00000040UL)
#define SWDT_CR_CKS_3                                  (0x00000080UL)
#define SWDT_CR_WDPT_POS                               (8U)
#define SWDT_CR_WDPT                                   (0x00000F00UL)
#define SWDT_CR_WDPT_0                                 (0x00000100UL)
#define SWDT_CR_WDPT_1                                 (0x00000200UL)
#define SWDT_CR_WDPT_2                                 (0x00000400UL)
#define SWDT_CR_WDPT_3                                 (0x00000800UL)
#define SWDT_CR_SLPOFF_POS                             (16U)
#define SWDT_CR_SLPOFF                                 (0x00010000UL)
#define SWDT_CR_ITS_POS                                (31U)
#define SWDT_CR_ITS                                    (0x80000000UL)

/*  Bit definition for SWDT_SR register  */
#define SWDT_SR_CNT_POS                                (0U)
#define SWDT_SR_CNT                                    (0x0000FFFFUL)
#define SWDT_SR_UDF_POS                                (16U)
#define SWDT_SR_UDF                                    (0x00010000UL)
#define SWDT_SR_REF_POS                                (17U)
#define SWDT_SR_REF                                    (0x00020000UL)

/*  Bit definition for SWDT_RR register  */
#define SWDT_RR_RF                                     (0x0000FFFFUL)

/*******************************************************************************
                Bit definition for Peripheral TMR0
*******************************************************************************/
/*  Bit definition for TMR0_CNTAR register  */
#define TMR0_CNTAR_CNTA                                (0x0000FFFFUL)

/*  Bit definition for TMR0_CMPAR register  */
#define TMR0_CMPAR_CMPA                                (0x0000FFFFUL)

/*  Bit definition for TMR0_BCONR register  */
#define TMR0_BCONR_CSTA_POS                            (0U)
#define TMR0_BCONR_CSTA                                (0x00000001UL)
#define TMR0_BCONR_CAPMDA_POS                          (1U)
#define TMR0_BCONR_CAPMDA                              (0x00000002UL)
#define TMR0_BCONR_INTENA_POS                          (2U)
#define TMR0_BCONR_INTENA                              (0x00000004UL)
#define TMR0_BCONR_CKDIVA_POS                          (4U)
#define TMR0_BCONR_CKDIVA                              (0x000000F0UL)
#define TMR0_BCONR_SYNSA_POS                           (8U)
#define TMR0_BCONR_SYNSA                               (0x00000100UL)
#define TMR0_BCONR_SYNCLKA_POS                         (9U)
#define TMR0_BCONR_SYNCLKA                             (0x00000200UL)
#define TMR0_BCONR_ASYNCLKA_POS                        (10U)
#define TMR0_BCONR_ASYNCLKA                            (0x00000400UL)
#define TMR0_BCONR_HSTAA_POS                           (12U)
#define TMR0_BCONR_HSTAA                               (0x00001000UL)
#define TMR0_BCONR_HSTPA_POS                           (13U)
#define TMR0_BCONR_HSTPA                               (0x00002000UL)
#define TMR0_BCONR_HCLEA_POS                           (14U)
#define TMR0_BCONR_HCLEA                               (0x00004000UL)
#define TMR0_BCONR_HICPA_POS                           (15U)
#define TMR0_BCONR_HICPA                               (0x00008000UL)

/*  Bit definition for TMR0_STFLR register  */
#define TMR0_STFLR_CMFA                                (0x00000001UL)

/*******************************************************************************
                Bit definition for Peripheral TMRB
*******************************************************************************/
/*  Bit definition for TMRB_CNTER register  */
#define TMRB_CNTER_CNT                                 (0xFFFFU)

/*  Bit definition for TMRB_PERAR register  */
#define TMRB_PERAR_PER                                 (0xFFFFU)

/*  Bit definition for TMRB_CMPAR register  */
#define TMRB_CMPAR_CMP                                 (0xFFFFU)

/*  Bit definition for TMRB_BCSTR register  */
#define TMRB_BCSTR_START_POS                           (0U)
#define TMRB_BCSTR_START                               (0x0001U)
#define TMRB_BCSTR_DIR_POS                             (1U)
#define TMRB_BCSTR_DIR                                 (0x0002U)
#define TMRB_BCSTR_MODE_POS                            (2U)
#define TMRB_BCSTR_MODE                                (0x0004U)
#define TMRB_BCSTR_SYNST_POS                           (3U)
#define TMRB_BCSTR_SYNST                               (0x0008U)
#define TMRB_BCSTR_CKDIV_POS                           (4U)
#define TMRB_BCSTR_CKDIV                               (0x00F0U)
#define TMRB_BCSTR_CKDIV_0                             (0x0010U)
#define TMRB_BCSTR_CKDIV_1                             (0x0020U)
#define TMRB_BCSTR_CKDIV_2                             (0x0040U)
#define TMRB_BCSTR_CKDIV_3                             (0x0080U)
#define TMRB_BCSTR_OVSTP_POS                           (8U)
#define TMRB_BCSTR_OVSTP                               (0x0100U)
#define TMRB_BCSTR_ITENOVF_POS                         (12U)
#define TMRB_BCSTR_ITENOVF                             (0x1000U)
#define TMRB_BCSTR_ITENUDF_POS                         (13U)
#define TMRB_BCSTR_ITENUDF                             (0x2000U)
#define TMRB_BCSTR_OVFF_POS                            (14U)
#define TMRB_BCSTR_OVFF                                (0x4000U)
#define TMRB_BCSTR_UDFF_POS                            (15U)
#define TMRB_BCSTR_UDFF                                (0x8000U)

/*  Bit definition for TMRB_HCONR register  */
#define TMRB_HCONR_HSTA0_POS                           (0U)
#define TMRB_HCONR_HSTA0                               (0x0001U)
#define TMRB_HCONR_HSTA1_POS                           (1U)
#define TMRB_HCONR_HSTA1                               (0x0002U)
#define TMRB_HCONR_HSTA2_POS                           (2U)
#define TMRB_HCONR_HSTA2                               (0x0004U)
#define TMRB_HCONR_HSTP0_POS                           (4U)
#define TMRB_HCONR_HSTP0                               (0x0010U)
#define TMRB_HCONR_HSTP1_POS                           (5U)
#define TMRB_HCONR_HSTP1                               (0x0020U)
#define TMRB_HCONR_HSTP2_POS                           (6U)
#define TMRB_HCONR_HSTP2                               (0x0040U)
#define TMRB_HCONR_HCLE0_POS                           (8U)
#define TMRB_HCONR_HCLE0                               (0x0100U)
#define TMRB_HCONR_HCLE1_POS                           (9U)
#define TMRB_HCONR_HCLE1                               (0x0200U)
#define TMRB_HCONR_HCLE2_POS                           (10U)
#define TMRB_HCONR_HCLE2                               (0x0400U)
#define TMRB_HCONR_HCLE3_POS                           (12U)
#define TMRB_HCONR_HCLE3                               (0x1000U)
#define TMRB_HCONR_HCLE4_POS                           (13U)
#define TMRB_HCONR_HCLE4                               (0x2000U)

/*  Bit definition for TMRB_HCUPR register  */
#define TMRB_HCUPR_HCUP8_POS                           (8U)
#define TMRB_HCUPR_HCUP8                               (0x0100U)
#define TMRB_HCUPR_HCUP9_POS                           (9U)
#define TMRB_HCUPR_HCUP9                               (0x0200U)
#define TMRB_HCUPR_HCUP10_POS                          (10U)
#define TMRB_HCUPR_HCUP10                              (0x0400U)
#define TMRB_HCUPR_HCUP11_POS                          (11U)
#define TMRB_HCUPR_HCUP11                              (0x0800U)
#define TMRB_HCUPR_HCUP12_POS                          (12U)
#define TMRB_HCUPR_HCUP12                              (0x1000U)

/*  Bit definition for TMRB_HCDOR register  */
#define TMRB_HCDOR_HCDO8_POS                           (8U)
#define TMRB_HCDOR_HCDO8                               (0x0100U)
#define TMRB_HCDOR_HCDO9_POS                           (9U)
#define TMRB_HCDOR_HCDO9                               (0x0200U)
#define TMRB_HCDOR_HCDO10_POS                          (10U)
#define TMRB_HCDOR_HCDO10                              (0x0400U)
#define TMRB_HCDOR_HCDO11_POS                          (11U)
#define TMRB_HCDOR_HCDO11                              (0x0800U)
#define TMRB_HCDOR_HCDO12_POS                          (12U)
#define TMRB_HCDOR_HCDO12                              (0x1000U)

/*  Bit definition for TMRB_ICONR register  */
#define TMRB_ICONR_ITEN1                               (0x0001U)

/*  Bit definition for TMRB_ECONR register  */
#define TMRB_ECONR_ETEN1                               (0x0001U)

/*  Bit definition for TMRB_STFLR register  */
#define TMRB_STFLR_CMPF1                               (0x0001U)

/*  Bit definition for TMRB_CCONR register  */
#define TMRB_CCONR_CAPMD_POS                           (0U)
#define TMRB_CCONR_CAPMD                               (0x0001U)
#define TMRB_CCONR_HICP0_POS                           (4U)
#define TMRB_CCONR_HICP0                               (0x0010U)
#define TMRB_CCONR_HICP1_POS                           (5U)
#define TMRB_CCONR_HICP1                               (0x0020U)
#define TMRB_CCONR_HICP2_POS                           (6U)
#define TMRB_CCONR_HICP2                               (0x0040U)
#define TMRB_CCONR_NOFIENCP_POS                        (12U)
#define TMRB_CCONR_NOFIENCP                            (0x1000U)
#define TMRB_CCONR_NOFICKCP_POS                        (13U)
#define TMRB_CCONR_NOFICKCP                            (0x6000U)
#define TMRB_CCONR_NOFICKCP_0                          (0x2000U)
#define TMRB_CCONR_NOFICKCP_1                          (0x4000U)

/*  Bit definition for TMRB_PCONR register  */
#define TMRB_PCONR_STAC_POS                            (0U)
#define TMRB_PCONR_STAC                                (0x0003U)
#define TMRB_PCONR_STAC_0                              (0x0001U)
#define TMRB_PCONR_STAC_1                              (0x0002U)
#define TMRB_PCONR_STPC_POS                            (2U)
#define TMRB_PCONR_STPC                                (0x000CU)
#define TMRB_PCONR_STPC_0                              (0x0004U)
#define TMRB_PCONR_STPC_1                              (0x0008U)
#define TMRB_PCONR_CMPC_POS                            (4U)
#define TMRB_PCONR_CMPC                                (0x0030U)
#define TMRB_PCONR_CMPC_0                              (0x0010U)
#define TMRB_PCONR_CMPC_1                              (0x0020U)
#define TMRB_PCONR_PERC_POS                            (6U)
#define TMRB_PCONR_PERC                                (0x00C0U)
#define TMRB_PCONR_PERC_0                              (0x0040U)
#define TMRB_PCONR_PERC_1                              (0x0080U)
#define TMRB_PCONR_FORC_POS                            (8U)
#define TMRB_PCONR_FORC                                (0x0300U)
#define TMRB_PCONR_FORC_0                              (0x0100U)
#define TMRB_PCONR_FORC_1                              (0x0200U)
#define TMRB_PCONR_OUTEN_POS                           (12U)
#define TMRB_PCONR_OUTEN                               (0x1000U)

/*******************************************************************************
                Bit definition for Peripheral USART
*******************************************************************************/
/*  Bit definition for USART_SR register  */
#define USART_SR_PE_POS                                (0U)
#define USART_SR_PE                                    (0x00000001UL)
#define USART_SR_FE_POS                                (1U)
#define USART_SR_FE                                    (0x00000002UL)
#define USART_SR_ORE_POS                               (3U)
#define USART_SR_ORE                                   (0x00000008UL)
#define USART_SR_RXNE_POS                              (5U)
#define USART_SR_RXNE                                  (0x00000020UL)
#define USART_SR_TC_POS                                (6U)
#define USART_SR_TC                                    (0x00000040UL)
#define USART_SR_TXE_POS                               (7U)
#define USART_SR_TXE                                   (0x00000080UL)
#define USART_SR_MPB_POS                               (16U)
#define USART_SR_MPB                                   (0x00010000UL)

/*  Bit definition for USART_DR register  */
#define USART_DR_TDR_POS                               (0U)
#define USART_DR_TDR                                   (0x000001FFUL)
#define USART_DR_MPID_POS                              (9U)
#define USART_DR_MPID                                  (0x00000200UL)
#define USART_DR_RDR_POS                               (16U)
#define USART_DR_RDR                                   (0x01FF0000UL)

/*  Bit definition for USART_BRR register  */
#define USART_BRR_DIV_INTEGER_POS                      (8U)
#define USART_BRR_DIV_INTEGER                          (0x0000FF00UL)

/*  Bit definition for USART_CR1 register  */
#define USART_CR1_RE_POS                               (2U)
#define USART_CR1_RE                                   (0x00000004UL)
#define USART_CR1_TE_POS                               (3U)
#define USART_CR1_TE                                   (0x00000008UL)
#define USART_CR1_SLME_POS                             (4U)
#define USART_CR1_SLME                                 (0x00000010UL)
#define USART_CR1_RIE_POS                              (5U)
#define USART_CR1_RIE                                  (0x00000020UL)
#define USART_CR1_TCIE_POS                             (6U)
#define USART_CR1_TCIE                                 (0x00000040UL)
#define USART_CR1_TXEIE_POS                            (7U)
#define USART_CR1_TXEIE                                (0x00000080UL)
#define USART_CR1_PS_POS                               (9U)
#define USART_CR1_PS                                   (0x00000200UL)
#define USART_CR1_PCE_POS                              (10U)
#define USART_CR1_PCE                                  (0x00000400UL)
#define USART_CR1_M_POS                                (12U)
#define USART_CR1_M                                    (0x00001000UL)
#define USART_CR1_OVER8_POS                            (15U)
#define USART_CR1_OVER8                                (0x00008000UL)
#define USART_CR1_CPE_POS                              (16U)
#define USART_CR1_CPE                                  (0x00010000UL)
#define USART_CR1_CFE_POS                              (17U)
#define USART_CR1_CFE                                  (0x00020000UL)
#define USART_CR1_CORE_POS                             (19U)
#define USART_CR1_CORE                                 (0x00080000UL)
#define USART_CR1_MS_POS                               (24U)
#define USART_CR1_MS                                   (0x01000000UL)
#define USART_CR1_ML_POS                               (28U)
#define USART_CR1_ML                                   (0x10000000UL)
#define USART_CR1_NFE_POS                              (30U)
#define USART_CR1_NFE                                  (0x40000000UL)
#define USART_CR1_SBS_POS                              (31U)
#define USART_CR1_SBS                                  (0x80000000UL)

/*  Bit definition for USART_CR2 register  */
#define USART_CR2_MPE_POS                              (0U)
#define USART_CR2_MPE                                  (0x00000001UL)
#define USART_CR2_CLKC_POS                             (11U)
#define USART_CR2_CLKC                                 (0x00001800UL)
#define USART_CR2_CLKC_0                               (0x00000800UL)
#define USART_CR2_CLKC_1                               (0x00001000UL)
#define USART_CR2_STOP_POS                             (13U)
#define USART_CR2_STOP                                 (0x00002000UL)
#define USART_CR2_LINEN_POS                            (14U)
#define USART_CR2_LINEN                                (0x00004000UL)

/*  Bit definition for USART_CR3 register  */
#define USART_CR3_HDSEL_POS                            (3U)
#define USART_CR3_HDSEL                                (0x00000008UL)
#define USART_CR3_CTSE_POS                             (9U)
#define USART_CR3_CTSE                                 (0x00000200UL)

/*  Bit definition for USART_PR register  */
#define USART_PR_PSC                                   (0x00000003UL)
#define USART_PR_PSC_0                                 (0x00000001UL)
#define USART_PR_PSC_1                                 (0x00000002UL)


/******************************************************************************/
/*             Device Specific Registers bit_band structure                   */
/******************************************************************************/

typedef struct
{
    __IO uint32_t STRT;
    uint32_t RESERVED0[7];
} stc_adc_str_bit_t;

typedef struct
{
    __IO uint32_t MS0;
    __IO uint32_t MS1;
    uint32_t RESERVED0[2];
    __IO uint32_t ACCSEL0;
    __IO uint32_t ACCSEL1;
    __IO uint32_t CLREN;
    __IO uint32_t DFMT;
    uint32_t RESERVED1[8];
} stc_adc_cr0_bit_t;

typedef struct
{
    uint32_t RESERVED0[2];
    __IO uint32_t RSCHSEL;
    uint32_t RESERVED1[13];
} stc_adc_cr1_bit_t;

typedef struct
{
    __IO uint32_t TRGSELA0;
    __IO uint32_t TRGSELA1;
    uint32_t RESERVED0[5];
    __IO uint32_t TRGENA;
    __IO uint32_t TRGSELB0;
    __IO uint32_t TRGSELB1;
    uint32_t RESERVED1[5];
    __IO uint32_t TRGENB;
} stc_adc_trgsr_bit_t;

typedef struct
{
    uint32_t RESERVED0[16];
} stc_adc_chselra0_bit_t;

typedef struct
{
    uint32_t RESERVED0[16];
} stc_adc_chselrb0_bit_t;

typedef struct
{
    __IO uint32_t EXCHSEL;
    uint32_t RESERVED0[7];
} stc_adc_exchselr_bit_t;

typedef struct
{
    __I  uint32_t EOCAF;
    __I  uint32_t EOCBF;
    uint32_t RESERVED0[6];
} stc_adc_isr_bit_t;

typedef struct
{
    __IO uint32_t EOCAIEN;
    __IO uint32_t EOCBIEN;
    uint32_t RESERVED0[6];
} stc_adc_icr_bit_t;

typedef struct
{
    __O  uint32_t CLREOCAF;
    __O  uint32_t CLREOCBF;
    uint32_t RESERVED0[6];
} stc_adc_isclrr_bit_t;

typedef struct
{
    __IO uint32_t AWD0EN;
    __IO uint32_t AWD0IEN;
    __IO uint32_t AWD0MD;
    uint32_t RESERVED0[1];
    __IO uint32_t AWD1EN;
    __IO uint32_t AWD1IEN;
    __IO uint32_t AWD1MD;
    uint32_t RESERVED1[1];
    __IO uint32_t AWDCM0;
    __IO uint32_t AWDCM1;
    uint32_t RESERVED2[6];
} stc_adc_awdcr_bit_t;

typedef struct
{
    __I  uint32_t AWD0F;
    __I  uint32_t AWD1F;
    uint32_t RESERVED0[2];
    __I  uint32_t AWDCMF;
    uint32_t RESERVED1[3];
} stc_adc_awdsr_bit_t;

typedef struct
{
    __O  uint32_t CLRAWD0F;
    __O  uint32_t CLRAWD1F;
    uint32_t RESERVED0[2];
    __O  uint32_t CLRAWDCMF;
    uint32_t RESERVED1[3];
} stc_adc_awdsclrr_bit_t;

typedef struct
{
    uint32_t RESERVED0[8];
} stc_adc_awd0chsr_bit_t;

typedef struct
{
    uint32_t RESERVED0[8];
} stc_adc_awd1chsr_bit_t;

typedef struct
{
    __O  uint32_t STRG;
    uint32_t RESERVED0[31];
} stc_aos_intc_strgcr_bit_t;

typedef struct
{
    __IO uint32_t PERICKSEL0;
    __IO uint32_t PERICKSEL1;
    __IO uint32_t PERICKSEL2;
    uint32_t RESERVED0[5];
} stc_cmu_pericksel_bit_t;

typedef struct
{
    __IO uint32_t XTALSTDF;
    uint32_t RESERVED0[7];
} stc_cmu_xtalstdsr_bit_t;

typedef struct
{
    __IO uint32_t SCKDIV0;
    __IO uint32_t SCKDIV1;
    __IO uint32_t SCKDIV2;
    uint32_t RESERVED0[5];
} stc_cmu_sckdivr_bit_t;

typedef struct
{
    __IO uint32_t CKSW0;
    __IO uint32_t CKSW1;
    uint32_t RESERVED0[6];
} stc_cmu_ckswr_bit_t;

typedef struct
{
    __IO uint32_t XTALSTP;
    uint32_t RESERVED0[7];
} stc_cmu_xtalcr_bit_t;

typedef struct
{
    uint32_t RESERVED0[4];
    __IO uint32_t XTALDRV0;
    __IO uint32_t XTALDRV1;
    __IO uint32_t XTALMS;
    __IO uint32_t SUPDRV;
} stc_cmu_xtalcfgr_bit_t;

typedef struct
{
    __IO uint32_t XTALSTB0;
    __IO uint32_t XTALSTB1;
    __IO uint32_t XTALSTB2;
    uint32_t RESERVED0[5];
} stc_cmu_xtalstbcr_bit_t;

typedef struct
{
    __IO uint32_t HRCSTP;
    uint32_t RESERVED0[7];
} stc_cmu_hrccr_bit_t;

typedef struct
{
    __I  uint32_t HRCSTBF;
    uint32_t RESERVED0[2];
    __I  uint32_t XTALSTBF;
    __I  uint32_t XTAL32STBF;
    uint32_t RESERVED1[3];
} stc_cmu_oscstbsr_bit_t;

typedef struct
{
    __IO uint32_t MCO1SEL0;
    __IO uint32_t MCO1SEL1;
    __IO uint32_t MCO1SEL2;
    __IO uint32_t MCO1SEL3;
    __IO uint32_t MCO1DIV0;
    __IO uint32_t MCO1DIV1;
    __IO uint32_t MCO1DIV2;
    __IO uint32_t MCO1EN;
} stc_cmu_mco1cfgr_bit_t;

typedef struct
{
    __IO uint32_t XTALSTDIE;
    __IO uint32_t XTALSTDRE;
    __IO uint32_t XTALSTDRIS;
    uint32_t RESERVED0[4];
    __IO uint32_t XTALSTDE;
} stc_cmu_xtalstdcr_bit_t;

typedef struct
{
    __IO uint32_t ADC;
    __IO uint32_t CTC;
    uint32_t RESERVED0[2];
    __IO uint32_t AOS;
    __IO uint32_t DMA;
    uint32_t RESERVED1[1];
    __IO uint32_t CRC;
    __IO uint32_t TIMB1;
    __IO uint32_t TIMB2;
    __IO uint32_t TIMB3;
    __IO uint32_t TIMB4;
    __IO uint32_t TIMB5;
    __IO uint32_t TIMB6;
    __IO uint32_t TIMB7;
    __IO uint32_t TIMB8;
    __IO uint32_t TIM0;
    uint32_t RESERVED2[6];
    __IO uint32_t RTC;
    __IO uint32_t UART1;
    __IO uint32_t UART2;
    __IO uint32_t UART3;
    __IO uint32_t UART4;
    __IO uint32_t I2C;
    __IO uint32_t SPI;
    __IO uint32_t UART5;
    __IO uint32_t UART6;
} stc_cmu_fcg_bit_t;

typedef struct
{
    __IO uint32_t XTAL32STP;
    uint32_t RESERVED0[7];
} stc_cmu_xtal32cr_bit_t;

typedef struct
{
    __IO uint32_t XTAL32DRV0;
    __IO uint32_t XTAL32DRV1;
    __IO uint32_t XTAL32DRV2;
    uint32_t RESERVED0[5];
} stc_cmu_xtal32cfgr_bit_t;

typedef struct
{
    __IO uint32_t XTAL32NF0;
    __IO uint32_t XTAL32NF1;
    uint32_t RESERVED0[6];
} stc_cmu_xtal32nfr_bit_t;

typedef struct
{
    __IO uint32_t LRCSTP;
    uint32_t RESERVED0[7];
} stc_cmu_lrccr_bit_t;

typedef struct
{
    __IO uint32_t CR;
    __IO uint32_t FLAG;
    uint32_t RESERVED0[30];
} stc_crc_cr_bit_t;

typedef struct
{
    __IO uint32_t REFPSC0;
    __IO uint32_t REFPSC1;
    __IO uint32_t REFPSC2;
    uint32_t RESERVED0[1];
    __IO uint32_t REFCKS0;
    __IO uint32_t REFCKS1;
    __IO uint32_t ERRIE;
    __IO uint32_t CTCEN;
    __IO uint32_t HRCPSC0;
    __IO uint32_t HRCPSC1;
    __IO uint32_t HRCPSC2;
    uint32_t RESERVED1[1];
    __IO uint32_t REFEDG0;
    __IO uint32_t REFEDG1;
    uint32_t RESERVED2[18];
} stc_ctc_cr1_bit_t;

typedef struct
{
    __I  uint32_t TRIMSUC;
    __I  uint32_t TRMOVF;
    __I  uint32_t TRMUDF;
    __I  uint32_t CTCBSY;
    uint32_t RESERVED0[28];
} stc_ctc_str_bit_t;

typedef struct
{
    uint32_t RESERVED0[16];
} stc_ctc_cnt_bit_t;

typedef struct
{
    __IO uint32_t CDBGPWRUPREQ;
    __IO uint32_t CDBGPWRUPACK;
    uint32_t RESERVED0[30];
} stc_dbgc_mcudbgstat_bit_t;

typedef struct
{
    __IO uint32_t SWDTSTP;
    uint32_t RESERVED0[1];
    __IO uint32_t RTCSTP;
    __IO uint32_t PVDSTP;
    uint32_t RESERVED1[10];
    __IO uint32_t TMR01STP;
    uint32_t RESERVED2[9];
    __IO uint32_t TMRB1STP;
    __IO uint32_t TMRB2STP;
    __IO uint32_t TMRB3STP;
    __IO uint32_t TMRB4STP;
    __IO uint32_t TMRB5STP;
    __IO uint32_t TMRB6STP;
    __IO uint32_t TMRB7STP;
    __IO uint32_t TMRB8STP;
} stc_dbgc_mcustpctl_bit_t;

typedef struct
{
    __IO uint32_t AUTH;
    __IO uint32_t REMVLOCK;
    __IO uint32_t SAFTYLOCK1;
    __IO uint32_t SAFTYLOCK2;
    uint32_t RESERVED0[4];
    __IO uint32_t MCUSTAT0;
    __IO uint32_t MCUSTAT1;
    uint32_t RESERVED1[22];
} stc_dbgc_t_mcustat_bit_t;

typedef struct
{
    __IO uint32_t EDBGRQ;
    __IO uint32_t RESTART;
    uint32_t RESERVED0[6];
    __IO uint32_t DIRQ;
    uint32_t RESERVED1[23];
} stc_dbgc_t_mcuctl_bit_t;

typedef struct
{
    __IO uint32_t ERASEREQ;
    __IO uint32_t ERASEACK;
    __IO uint32_t ERASEERR;
    uint32_t RESERVED0[29];
} stc_dbgc_t_fmcctl_bit_t;

typedef struct
{
    __IO uint32_t EN;
    uint32_t RESERVED0[31];
} stc_dma_en_bit_t;

typedef struct
{
    __I  uint32_t TRNERR0;
    __I  uint32_t TRNERR1;
    uint32_t RESERVED0[14];
    __I  uint32_t REQERR0;
    __I  uint32_t REQERR1;
    uint32_t RESERVED1[14];
} stc_dma_intstat0_bit_t;

typedef struct
{
    __I  uint32_t TC0;
    __I  uint32_t TC1;
    uint32_t RESERVED0[14];
    __I  uint32_t BTC0;
    __I  uint32_t BTC1;
    uint32_t RESERVED1[14];
} stc_dma_intstat1_bit_t;

typedef struct
{
    __IO uint32_t MSKTRNERR0;
    __IO uint32_t MSKTRNERR1;
    uint32_t RESERVED0[14];
    __IO uint32_t MSKREQERR0;
    __IO uint32_t MSKREQERR1;
    uint32_t RESERVED1[14];
} stc_dma_intmask0_bit_t;

typedef struct
{
    __IO uint32_t MSKTC0;
    __IO uint32_t MSKTC1;
    uint32_t RESERVED0[14];
    __IO uint32_t MSKBTC0;
    __IO uint32_t MSKBTC1;
    uint32_t RESERVED1[14];
} stc_dma_intmask1_bit_t;

typedef struct
{
    __O  uint32_t CLRTRNERR0;
    __O  uint32_t CLRTRNERR1;
    uint32_t RESERVED0[14];
    __O  uint32_t CLRREQERR0;
    __O  uint32_t CLRREQERR1;
    uint32_t RESERVED1[14];
} stc_dma_intclr0_bit_t;

typedef struct
{
    __O  uint32_t CLRTC0;
    __O  uint32_t CLRTC1;
    uint32_t RESERVED0[14];
    __O  uint32_t CLRBTC0;
    __O  uint32_t CLRBTC1;
    uint32_t RESERVED1[14];
} stc_dma_intclr1_bit_t;

typedef struct
{
    __IO uint32_t CHEN0;
    __IO uint32_t CHEN1;
    uint32_t RESERVED0[30];
} stc_dma_chen_bit_t;

typedef struct
{
    __I  uint32_t DMAACT;
    uint32_t RESERVED0[15];
    __I  uint32_t CHACT0;
    __I  uint32_t CHACT1;
    uint32_t RESERVED1[14];
} stc_dma_chstat_bit_t;

typedef struct
{
    __IO uint32_t CHENCLR0;
    __IO uint32_t CHENCLR1;
    uint32_t RESERVED0[30];
} stc_dma_chenclr_bit_t;

typedef struct
{
    uint32_t RESERVED0[28];
    __IO uint32_t LLPEN;
    __IO uint32_t LLPRUN;
    __IO uint32_t HSIZE0;
    __IO uint32_t HSIZE1;
} stc_dma_ch0ctl0_bit_t;

typedef struct
{
    uint32_t RESERVED0[24];
    __IO uint32_t RPTNSEN;
    __IO uint32_t RPTNSSEL0;
    __IO uint32_t RPTNSSEL1;
    __IO uint32_t LLPSEL;
    __IO uint32_t SINC0;
    __IO uint32_t SINC1;
    __IO uint32_t DINC0;
    __IO uint32_t DINC1;
} stc_dma_ch0ctl1_bit_t;

typedef struct
{
    uint32_t RESERVED0[28];
    __IO uint32_t LLPEN;
    __IO uint32_t LLPRUN;
    __IO uint32_t HSIZE0;
    __IO uint32_t HSIZE1;
} stc_dma_ch1ctl0_bit_t;

typedef struct
{
    uint32_t RESERVED0[24];
    __IO uint32_t RPTNSEN;
    __IO uint32_t RPTNSSEL0;
    __IO uint32_t RPTNSSEL1;
    __IO uint32_t LLPSEL;
    __IO uint32_t SINC0;
    __IO uint32_t SINC1;
    __IO uint32_t DINC0;
    __IO uint32_t DINC1;
} stc_dma_ch1ctl1_bit_t;

typedef struct
{
    __IO uint32_t FSTP;
    uint32_t RESERVED0[31];
} stc_efm_fstp_bit_t;

typedef struct
{
    __IO uint32_t FLWT0;
    __IO uint32_t FLWT1;
    uint32_t RESERVED0[15];
    __IO uint32_t PREFETE;
    uint32_t RESERVED1[14];
} stc_efm_frmc_bit_t;

typedef struct
{
    __IO uint32_t PEMODE;
    uint32_t RESERVED0[3];
    __IO uint32_t PEMOD0;
    __IO uint32_t PEMOD1;
    __IO uint32_t PEMOD2;
    uint32_t RESERVED1[1];
    __IO uint32_t BUSHLDCTL;
    uint32_t RESERVED2[7];
    __IO uint32_t ERCALE;
    uint32_t RESERVED3[15];
} stc_efm_fwmc_bit_t;

typedef struct
{
    __I  uint32_t PEWERR;
    __I  uint32_t PEPRTERR;
    uint32_t RESERVED0[1];
    __I  uint32_t PGMISMTCH;
    __I  uint32_t OPTEND;
    __I  uint32_t COLERR;
    __IO uint32_t ERCAL;
    uint32_t RESERVED1[1];
    __I  uint32_t RDY;
    uint32_t RESERVED2[23];
} stc_efm_fsr_bit_t;

typedef struct
{
    __IO uint32_t PEWERRCLR;
    __IO uint32_t PEPRTERRCLR;
    uint32_t RESERVED0[1];
    __IO uint32_t PGMISMTCHCLR;
    __IO uint32_t OPTENDCLR;
    __IO uint32_t COLERRCLR;
    __IO uint32_t ERCALCLR;
    uint32_t RESERVED1[25];
} stc_efm_fsclr_bit_t;

typedef struct
{
    __IO uint32_t PEERRITE;
    __IO uint32_t OPTENDITE;
    __IO uint32_t COLERRITE;
    uint32_t RESERVED0[29];
} stc_efm_fite_bit_t;

typedef struct
{
    __IO uint32_t HRCFREQS0;
    __IO uint32_t HRCFREQS1;
    __IO uint32_t HRCFREQS2;
    __IO uint32_t HRCFREQS3;
    uint32_t RESERVED0[4];
} stc_efm_cmu_hrccfgr_bit_t;

typedef struct
{
    __IO uint32_t DFS0;
    __IO uint32_t DFS1;
    __IO uint32_t DFDIS;
    uint32_t RESERVED0[5];
    __IO uint32_t LVDLVL0;
    __IO uint32_t LVDLVL1;
    __IO uint32_t LVDLVL2;
    __IO uint32_t LVDLVL3;
    __IO uint32_t NMIS;
    __IO uint32_t IRS;
    __IO uint32_t IRDIS;
    __IO uint32_t LVDDIS;
} stc_efm_pwc_lvdicgcr_bit_t;

typedef struct
{
    __I  uint32_t PIN0;
    __I  uint32_t PIN1;
    __I  uint32_t PIN2;
    __I  uint32_t PIN3;
    __I  uint32_t PIN4;
    __I  uint32_t PIN5;
    __I  uint32_t PIN6;
    __I  uint32_t PIN7;
} stc_gpio_pidr_bit_t;

typedef struct
{
    __IO uint32_t POUT0;
    __IO uint32_t POUT1;
    __IO uint32_t POUT2;
    __IO uint32_t POUT3;
    __IO uint32_t POUT4;
    __IO uint32_t POUT5;
    __IO uint32_t POUT6;
    __IO uint32_t POUT7;
} stc_gpio_podr_bit_t;

typedef struct
{
    __IO uint32_t POUTE0;
    __IO uint32_t POUTE1;
    __IO uint32_t POUTE2;
    __IO uint32_t POUTE3;
    __IO uint32_t POUTE4;
    __IO uint32_t POUTE5;
    __IO uint32_t POUTE6;
    __IO uint32_t POUTE7;
} stc_gpio_poer_bit_t;

typedef struct
{
    __O  uint32_t POS0;
    __O  uint32_t POS1;
    __O  uint32_t POS2;
    __O  uint32_t POS3;
    __O  uint32_t POS4;
    __O  uint32_t POS5;
    __O  uint32_t POS6;
    __O  uint32_t POS7;
} stc_gpio_posr_bit_t;

typedef struct
{
    __O  uint32_t POR0;
    __O  uint32_t POR1;
    __O  uint32_t POR2;
    __O  uint32_t POR3;
    __O  uint32_t POR4;
    __O  uint32_t POR5;
    __O  uint32_t POR6;
    __O  uint32_t POR7;
} stc_gpio_porr_bit_t;

typedef struct
{
    __O  uint32_t POT0;
    __O  uint32_t POT1;
    __O  uint32_t POT2;
    __O  uint32_t POT3;
    __O  uint32_t POT4;
    __O  uint32_t POT5;
    __O  uint32_t POT6;
    __O  uint32_t POT7;
} stc_gpio_potr_bit_t;

typedef struct
{
    __IO uint32_t POUT;
    __IO uint32_t POUTE;
    __IO uint32_t NOD;
    uint32_t RESERVED0[1];
    __IO uint32_t DRV;
    __IO uint32_t LTE;
    __IO uint32_t PUU;
    uint32_t RESERVED1[1];
    __I  uint32_t PIN;
    __IO uint32_t INVE;
    __IO uint32_t CINSEL;
    __IO uint32_t INTE;
    uint32_t RESERVED2[4];
} stc_gpio_pcr_bit_t;

typedef struct
{
    __IO uint32_t SPFE0;
    __IO uint32_t SPFE1;
    uint32_t RESERVED0[14];
} stc_gpio_pspcr_bit_t;

typedef struct
{
    uint32_t RESERVED0[14];
    __IO uint32_t RDWT0;
    __IO uint32_t RDWT1;
} stc_gpio_pccr_bit_t;

typedef struct
{
    __IO uint32_t PINAE0;
    __IO uint32_t PINAE1;
    __IO uint32_t PINAE2;
    __IO uint32_t PINAE3;
    __IO uint32_t PINAE4;
    __IO uint32_t PINAE5;
    __IO uint32_t PINAE6;
    __IO uint32_t PINAE7;
    uint32_t RESERVED0[4];
    __IO uint32_t PINAE12;
    __IO uint32_t PINAE13;
    __IO uint32_t PINAE14;
    uint32_t RESERVED1[1];
} stc_gpio_pinaer_bit_t;

typedef struct
{
    __IO uint32_t WE;
    uint32_t RESERVED0[15];
} stc_gpio_pwpr_bit_t;

typedef struct
{
    __IO uint32_t PE;
    __IO uint32_t SMBUS;
    __IO uint32_t SMBALRTEN;
    __IO uint32_t SMBDEFAULTEN;
    __IO uint32_t SMBHOSTEN;
    __IO uint32_t FACKEN;
    __IO uint32_t GCEN;
    __IO uint32_t RESTART;
    __IO uint32_t START;
    __IO uint32_t STOP;
    __IO uint32_t ACK;
    uint32_t RESERVED0[4];
    __IO uint32_t SWRST;
    uint32_t RESERVED1[16];
} stc_i2c_cr1_bit_t;

typedef struct
{
    __IO uint32_t STARTIE;
    __IO uint32_t SLADDR0IE;
    __IO uint32_t SLADDR1IE;
    __IO uint32_t TENDIE;
    __IO uint32_t STOPIE;
    uint32_t RESERVED0[1];
    __IO uint32_t RFULLIE;
    __IO uint32_t TEMPTYIE;
    uint32_t RESERVED1[1];
    __IO uint32_t ARLOIE;
    uint32_t RESERVED2[2];
    __IO uint32_t NACKIE;
    uint32_t RESERVED3[7];
    __IO uint32_t GENCALLIE;
    __IO uint32_t SMBDEFAULTIE;
    __IO uint32_t SMBHOSTIE;
    __IO uint32_t SMBALRTIE;
    uint32_t RESERVED4[8];
} stc_i2c_cr2_bit_t;

typedef struct
{
    uint32_t RESERVED0[12];
    __IO uint32_t SLADDR0EN;
    uint32_t RESERVED1[2];
    __IO uint32_t ADDRMOD0;
    uint32_t RESERVED2[16];
} stc_i2c_slr0_bit_t;

typedef struct
{
    uint32_t RESERVED0[12];
    __IO uint32_t SLADDR1EN;
    uint32_t RESERVED1[2];
    __IO uint32_t ADDRMOD1;
    uint32_t RESERVED2[16];
} stc_i2c_slr1_bit_t;

typedef struct
{
    __I  uint32_t STARTF;
    __I  uint32_t SLADDR0F;
    __I  uint32_t SLADDR1F;
    __I  uint32_t TENDF;
    __I  uint32_t STOPF;
    uint32_t RESERVED0[1];
    __I  uint32_t RFULLF;
    __I  uint32_t TEMPTYF;
    uint32_t RESERVED1[1];
    __I  uint32_t ARLOF;
    __I  uint32_t ACKRF;
    uint32_t RESERVED2[1];
    __I  uint32_t NACKF;
    uint32_t RESERVED3[3];
    __IO uint32_t MSL;
    __I  uint32_t BUSY;
    __IO uint32_t TRA;
    uint32_t RESERVED4[1];
    __I  uint32_t GENCALLF;
    __I  uint32_t SMBDEFAULTF;
    __I  uint32_t SMBHOSTF;
    __I  uint32_t SMBALRTF;
    uint32_t RESERVED5[8];
} stc_i2c_sr_bit_t;

typedef struct
{
    __O  uint32_t STARTFCLR;
    __O  uint32_t SLADDR0FCLR;
    __O  uint32_t SLADDR1FCLR;
    __O  uint32_t TENDFCLR;
    __O  uint32_t STOPFCLR;
    uint32_t RESERVED0[1];
    __O  uint32_t RFULLFCLR;
    __O  uint32_t TEMPTYFCLR;
    uint32_t RESERVED1[1];
    __O  uint32_t ARLOFCLR;
    uint32_t RESERVED2[2];
    __O  uint32_t NACKFCLR;
    uint32_t RESERVED3[7];
    __O  uint32_t GENCALLFCLR;
    __O  uint32_t SMBDEFAULTFCLR;
    __O  uint32_t SMBHOSTFCLR;
    __O  uint32_t SMBALRTFCLR;
    uint32_t RESERVED4[8];
} stc_i2c_clr_bit_t;

typedef struct
{
    uint32_t RESERVED0[8];
} stc_i2c_dtr_bit_t;

typedef struct
{
    uint32_t RESERVED0[8];
} stc_i2c_drr_bit_t;

typedef struct
{
    uint32_t RESERVED0[16];
    __IO uint32_t CKDIV0;
    __IO uint32_t CKDIV1;
    __IO uint32_t CKDIV2;
    uint32_t RESERVED1[13];
} stc_i2c_ccr_bit_t;

typedef struct
{
    __IO uint32_t DNF0;
    __IO uint32_t DNF1;
    uint32_t RESERVED0[2];
    __IO uint32_t DNFEN;
    uint32_t RESERVED1[27];
} stc_i2c_fltr_bit_t;

typedef struct
{
    __I  uint32_t SWDTAUTS;
    __I  uint32_t SWDTITS;
    __I  uint32_t SWDTPERI0;
    __I  uint32_t SWDTPERI1;
    uint32_t RESERVED0[8];
    __I  uint32_t SWDTSLPOFF;
    uint32_t RESERVED1[19];
} stc_icg_icg0_bit_t;

typedef struct
{
    __I  uint32_t DFS0;
    __I  uint32_t DFS1;
    __I  uint32_t DFDIS;
    uint32_t RESERVED0[9];
    __I  uint32_t NMIS;
    __I  uint32_t IRS;
    __I  uint32_t IRDIS;
    __I  uint32_t LVDDIS;
    __I  uint32_t LKUPDIS;
    uint32_t RESERVED1[15];
} stc_icg_icg1_bit_t;

typedef struct
{
    uint32_t RESERVED0[1];
    __IO uint32_t XTALSTPEN;
    __IO uint32_t SWDTEN;
    __IO uint32_t PVDEN;
    uint32_t RESERVED1[28];
} stc_intc_nmier_bit_t;

typedef struct
{
    uint32_t RESERVED0[1];
    __I  uint32_t XTALSTPF;
    __I  uint32_t SWDTF;
    __I  uint32_t PVDF;
    uint32_t RESERVED1[28];
} stc_intc_nmifr_bit_t;

typedef struct
{
    uint32_t RESERVED0[1];
    __IO uint32_t XTALSTPCL;
    __IO uint32_t SWDTCL;
    __IO uint32_t PVDCL;
    uint32_t RESERVED1[28];
} stc_intc_nmiclr_bit_t;

typedef struct
{
    __IO uint32_t EVTEN0;
    __IO uint32_t EVTEN1;
    __IO uint32_t EVTEN2;
    __IO uint32_t EVTEN3;
    __IO uint32_t EVTEN4;
    __IO uint32_t EVTEN5;
    __IO uint32_t EVTEN6;
    __IO uint32_t EVTEN7;
    uint32_t RESERVED0[24];
} stc_intc_evter_bit_t;

typedef struct
{
    __IO uint32_t EKEY0EN;
    __IO uint32_t EKEY1EN;
    __IO uint32_t EKEY2EN;
    __IO uint32_t EKEY3EN;
    __IO uint32_t EKEY4EN;
    __IO uint32_t EKEY5EN;
    __IO uint32_t EKEY6EN;
    __IO uint32_t EKEY7EN;
    uint32_t RESERVED0[24];
} stc_intc_ekeycr_bit_t;

typedef struct
{
    __IO uint32_t FPRC0;
    __IO uint32_t FPRC1;
    __IO uint32_t FPRC2;
    __IO uint32_t FPRC3;
    __IO uint32_t FPRC4;
    __IO uint32_t FPRC5;
    __IO uint32_t FPRC6;
    __IO uint32_t FPRC7;
    uint32_t RESERVED0[24];
} stc_intc_fprcr_bit_t;

typedef struct
{
    __IO uint32_t EIRQTRG0;
    __IO uint32_t EIRQTRG1;
    uint32_t RESERVED0[2];
    __IO uint32_t EIRQFCLK0;
    __IO uint32_t EIRQFCLK1;
    uint32_t RESERVED1[1];
    __IO uint32_t EIRQFEN;
    uint32_t RESERVED2[24];
} stc_intc_eirqcr_bit_t;

typedef struct
{
    __IO uint32_t EIRQWUEN0;
    __IO uint32_t EIRQWUEN1;
    __IO uint32_t EIRQWUEN2;
    __IO uint32_t EIRQWUEN3;
    __IO uint32_t EIRQWUEN4;
    __IO uint32_t EIRQWUEN5;
    __IO uint32_t EIRQWUEN6;
    __IO uint32_t EIRQWUEN7;
    __IO uint32_t EIRQWUEN8;
    __IO uint32_t EIRQWUEN9;
    __IO uint32_t EIRQWUEN10;
    __IO uint32_t EIRQWUEN11;
    uint32_t RESERVED0[4];
    __IO uint32_t SWDTWUEN;
    __IO uint32_t EKEYWUEN;
    __IO uint32_t TMR0CMPWUEN;
    uint32_t RESERVED1[3];
    __IO uint32_t PVDWUEN;
    __IO uint32_t RTCALMWUEN;
    __IO uint32_t RTCPRDWUEN;
    uint32_t RESERVED2[7];
} stc_intc_wupenr_bit_t;

typedef struct
{
    __IO uint32_t EIRQF0;
    __IO uint32_t EIRQF1;
    __IO uint32_t EIRQF2;
    __IO uint32_t EIRQF3;
    __IO uint32_t EIRQF4;
    __IO uint32_t EIRQF5;
    __IO uint32_t EIRQF6;
    __IO uint32_t EIRQF7;
    __IO uint32_t EIRQF8;
    __IO uint32_t EIRQF9;
    __IO uint32_t EIRQF10;
    __IO uint32_t EIRQF11;
    uint32_t RESERVED0[20];
} stc_intc_eirqfr_bit_t;

typedef struct
{
    __IO uint32_t EIRQCL0;
    __IO uint32_t EIRQCL1;
    __IO uint32_t EIRQCL2;
    __IO uint32_t EIRQCL3;
    __IO uint32_t EIRQCL4;
    __IO uint32_t EIRQCL5;
    __IO uint32_t EIRQCL6;
    __IO uint32_t EIRQCL7;
    __IO uint32_t EIRQCL8;
    __IO uint32_t EIRQCL9;
    __IO uint32_t EIRQCL10;
    __IO uint32_t EIRQCL11;
    uint32_t RESERVED0[20];
} stc_intc_eirqclr_bit_t;

typedef struct
{
    uint32_t RESERVED0[1];
    __IO uint32_t ISEL1;
    __IO uint32_t ISEL2;
    __IO uint32_t ISEL3;
    __IO uint32_t ISEL4;
    __IO uint32_t ISEL5;
    __IO uint32_t ISEL6;
    __IO uint32_t ISEL7;
    __IO uint32_t ISEL8;
    __IO uint32_t ISEL9;
    __IO uint32_t ISEL10;
    __IO uint32_t ISEL11;
    __IO uint32_t ISEL12;
    __IO uint32_t ISEL13;
    __IO uint32_t ISEL14;
    __IO uint32_t ISEL15;
    uint32_t RESERVED1[16];
} stc_intc_iselbr_bit_t;

typedef struct
{
    __IO uint32_t FLNWT;
    __IO uint32_t CKSHRC;
    uint32_t RESERVED0[1];
    __IO uint32_t HAPORDIS;
    uint32_t RESERVED1[3];
    __IO uint32_t STOP;
} stc_pwc_stpmcr_bit_t;

typedef struct
{
    __IO uint32_t PWDRV0;
    __IO uint32_t PWDRV1;
    __IO uint32_t PWDRV2;
    __IO uint32_t DVS;
    uint32_t RESERVED0[2];
    __IO uint32_t VHRCE;
    __IO uint32_t HRCPWRDY;
} stc_pwc_pwrc_bit_t;

typedef struct
{
    __IO uint32_t PWMONSEL;
    __IO uint32_t PWMONE;
    uint32_t RESERVED0[6];
} stc_pwc_pwrmon_bit_t;

typedef struct
{
    __IO uint32_t RPRTA0;
    __IO uint32_t RPRTA1;
    uint32_t RESERVED0[2];
    __IO uint32_t RPERDIS;
    __IO uint32_t RPERF;
    uint32_t RESERVED1[2];
} stc_pwc_ramcr_bit_t;

typedef struct
{
    __IO uint32_t EXVCCINEN;
    uint32_t RESERVED0[2];
    __IO uint32_t LVIF;
    __IO uint32_t DETF;
    uint32_t RESERVED1[2];
    __IO uint32_t CMPOE;
} stc_pwc_lvdcsr_bit_t;

typedef struct
{
    __IO uint32_t CKRWE;
    __IO uint32_t PWRWE;
    __IO uint32_t FPRCB2;
    __IO uint32_t LVRWE;
    __IO uint32_t FPRCB4;
    __IO uint32_t FPRCB5;
    __IO uint32_t FPRCB6;
    __IO uint32_t FPRCB7;
    __O  uint32_t FPRCWE0;
    __O  uint32_t FPRCWE1;
    __O  uint32_t FPRCWE2;
    __O  uint32_t FPRCWE3;
    __O  uint32_t FPRCWE4;
    __O  uint32_t FPRCWE5;
    __O  uint32_t FPRCWE6;
    __O  uint32_t FPRCWE7;
} stc_pwc_fprc_bit_t;

typedef struct
{
    __IO uint32_t DBGEN;
    __I  uint32_t DBGWKF;
    uint32_t RESERVED0[6];
} stc_pwc_dbgc_bit_t;

typedef struct
{
    __IO uint32_t PORF;
    __IO uint32_t PINRF;
    __IO uint32_t LVRF;
    uint32_t RESERVED0[2];
    __IO uint32_t WDRF;
    uint32_t RESERVED1[2];
    __IO uint32_t SWRF;
    uint32_t RESERVED2[1];
    __IO uint32_t RAMPERF;
    uint32_t RESERVED3[1];
    __IO uint32_t CPULKUPRF;
    __IO uint32_t XTALERF;
    __IO uint32_t MULTIRF;
    __IO uint32_t CLRF;
} stc_rmu_rstf0_bit_t;

typedef struct
{
    __IO uint32_t RESET;
    uint32_t RESERVED0[7];
} stc_rtc_cr0_bit_t;

typedef struct
{
    uint32_t RESERVED0[3];
    __IO uint32_t AMPM;
    uint32_t RESERVED1[1];
    __IO uint32_t ONEHZOE;
    uint32_t RESERVED2[1];
    __IO uint32_t START;
} stc_rtc_cr1_bit_t;

typedef struct
{
    __IO uint32_t RWREQ;
    __IO uint32_t RWEN;
    __IO uint32_t PRDF;
    __IO uint32_t ALMF;
    uint32_t RESERVED0[1];
    __IO uint32_t PRDIE;
    __IO uint32_t ALMIE;
    __IO uint32_t ALME;
} stc_rtc_cr2_bit_t;

typedef struct
{
    uint32_t RESERVED0[4];
    __IO uint32_t LRCEN;
    uint32_t RESERVED1[2];
    __IO uint32_t RCKSEL;
} stc_rtc_cr3_bit_t;

typedef struct
{
    uint32_t RESERVED0[8];
} stc_rtc_sec_bit_t;

typedef struct
{
    uint32_t RESERVED0[8];
} stc_rtc_min_bit_t;

typedef struct
{
    uint32_t RESERVED0[4];
    __IO uint32_t HOURD0;
    __IO uint32_t HOURD1;
    uint32_t RESERVED1[2];
} stc_rtc_hour_bit_t;

typedef struct
{
    uint32_t RESERVED0[8];
} stc_rtc_week_bit_t;

typedef struct
{
    uint32_t RESERVED0[8];
} stc_rtc_day_bit_t;

typedef struct
{
    uint32_t RESERVED0[8];
} stc_rtc_mon_bit_t;

typedef struct
{
    uint32_t RESERVED0[8];
} stc_rtc_year_bit_t;

typedef struct
{
    uint32_t RESERVED0[8];
} stc_rtc_almmin_bit_t;

typedef struct
{
    uint32_t RESERVED0[4];
    __IO uint32_t ALMHOURD0;
    __IO uint32_t ALMHOURD1;
    uint32_t RESERVED1[2];
} stc_rtc_almhour_bit_t;

typedef struct
{
    __IO uint32_t ALMWEEK0;
    __IO uint32_t ALMWEEK1;
    __IO uint32_t ALMWEEK2;
    __IO uint32_t ALMWEEK3;
    __IO uint32_t ALMWEEK4;
    __IO uint32_t ALMWEEK5;
    __IO uint32_t ALMWEEK6;
    uint32_t RESERVED0[1];
} stc_rtc_almweek_bit_t;

typedef struct
{
    __IO uint32_t COMP8;
    uint32_t RESERVED0[6];
    __IO uint32_t COMPEN;
} stc_rtc_errcrh_bit_t;

typedef struct
{
    uint32_t RESERVED0[8];
} stc_rtc_errcrl_bit_t;

typedef struct
{
    __IO uint32_t SPIMDS;
    __IO uint32_t TXMDS;
    uint32_t RESERVED0[1];
    __IO uint32_t MSTR;
    __IO uint32_t SPLPBK;
    __IO uint32_t SPLPBK2;
    __IO uint32_t SPE;
    uint32_t RESERVED1[1];
    __IO uint32_t EIE;
    __IO uint32_t TXIE;
    __IO uint32_t RXIE;
    __IO uint32_t IDIE;
    __IO uint32_t MODFE;
    __IO uint32_t PATE;
    __IO uint32_t PAOE;
    __IO uint32_t PAE;
    uint32_t RESERVED2[16];
} stc_spi_cr1_bit_t;

typedef struct
{
    uint32_t RESERVED0[8];
    __IO uint32_t SS0PV;
    uint32_t RESERVED1[23];
} stc_spi_cfg1_bit_t;

typedef struct
{
    __IO uint32_t OVRERF;
    __I  uint32_t IDLNF;
    __IO uint32_t MODFERF;
    __IO uint32_t PERF;
    __IO uint32_t UDRERF;
    __IO uint32_t TDEF;
    uint32_t RESERVED0[1];
    __IO uint32_t RDFF;
    uint32_t RESERVED1[24];
} stc_spi_sr_bit_t;

typedef struct
{
    __IO uint32_t CPHA;
    __IO uint32_t CPOL;
    __IO uint32_t MBR0;
    __IO uint32_t MBR1;
    __IO uint32_t MBR2;
    uint32_t RESERVED0[3];
    __IO uint32_t DSIZE;
    uint32_t RESERVED1[3];
    __IO uint32_t LSBF;
    uint32_t RESERVED2[19];
} stc_spi_cfg2_bit_t;

typedef struct
{
    __IO uint32_t PERI0;
    __IO uint32_t PERI1;
    uint32_t RESERVED0[2];
    __IO uint32_t CKS0;
    __IO uint32_t CKS1;
    __IO uint32_t CKS2;
    __IO uint32_t CKS3;
    __IO uint32_t WDPT0;
    __IO uint32_t WDPT1;
    __IO uint32_t WDPT2;
    __IO uint32_t WDPT3;
    uint32_t RESERVED1[4];
    __IO uint32_t SLPOFF;
    uint32_t RESERVED2[14];
    __IO uint32_t ITS;
} stc_swdt_cr_bit_t;

typedef struct
{
    uint32_t RESERVED0[16];
    __IO uint32_t UDF;
    __IO uint32_t REF;
    uint32_t RESERVED1[14];
} stc_swdt_sr_bit_t;

typedef struct
{
    __IO uint32_t CSTA;
    __IO uint32_t CAPMDA;
    __IO uint32_t INTENA;
    uint32_t RESERVED0[5];
    __IO uint32_t SYNSA;
    __IO uint32_t SYNCLKA;
    __IO uint32_t ASYNCLKA;
    uint32_t RESERVED1[1];
    __IO uint32_t HSTAA;
    __IO uint32_t HSTPA;
    __IO uint32_t HCLEA;
    __IO uint32_t HICPA;
    uint32_t RESERVED2[16];
} stc_tmr0_bconr_bit_t;

typedef struct
{
    __IO uint32_t CMFA;
    uint32_t RESERVED0[31];
} stc_tmr0_stflr_bit_t;

typedef struct
{
    uint32_t RESERVED0[16];
} stc_tmrb_cnter_bit_t;

typedef struct
{
    uint32_t RESERVED0[16];
} stc_tmrb_perar_bit_t;

typedef struct
{
    uint32_t RESERVED0[16];
} stc_tmrb_cmpar_bit_t;

typedef struct
{
    __IO uint32_t START;
    __IO uint32_t DIR;
    __IO uint32_t MODE;
    __IO uint32_t SYNST;
    __IO uint32_t CKDIV0;
    __IO uint32_t CKDIV1;
    __IO uint32_t CKDIV2;
    __IO uint32_t CKDIV3;
    __IO uint32_t OVSTP;
    uint32_t RESERVED0[3];
    __IO uint32_t ITENOVF;
    __IO uint32_t ITENUDF;
    __IO uint32_t OVFF;
    __IO uint32_t UDFF;
} stc_tmrb_bcstr_bit_t;

typedef struct
{
    __IO uint32_t HSTA0;
    __IO uint32_t HSTA1;
    __IO uint32_t HSTA2;
    uint32_t RESERVED0[1];
    __IO uint32_t HSTP0;
    __IO uint32_t HSTP1;
    __IO uint32_t HSTP2;
    uint32_t RESERVED1[1];
    __IO uint32_t HCLE0;
    __IO uint32_t HCLE1;
    __IO uint32_t HCLE2;
    uint32_t RESERVED2[1];
    __IO uint32_t HCLE3;
    __IO uint32_t HCLE4;
    uint32_t RESERVED3[2];
} stc_tmrb_hconr_bit_t;

typedef struct
{
    uint32_t RESERVED0[8];
    __IO uint32_t HCUP8;
    __IO uint32_t HCUP9;
    __IO uint32_t HCUP10;
    __IO uint32_t HCUP11;
    __IO uint32_t HCUP12;
    uint32_t RESERVED1[3];
} stc_tmrb_hcupr_bit_t;

typedef struct
{
    uint32_t RESERVED0[8];
    __IO uint32_t HCDO8;
    __IO uint32_t HCDO9;
    __IO uint32_t HCDO10;
    __IO uint32_t HCDO11;
    __IO uint32_t HCDO12;
    uint32_t RESERVED1[3];
} stc_tmrb_hcdor_bit_t;

typedef struct
{
    __IO uint32_t ITEN1;
    uint32_t RESERVED0[15];
} stc_tmrb_iconr_bit_t;

typedef struct
{
    __IO uint32_t ETEN1;
    uint32_t RESERVED0[15];
} stc_tmrb_econr_bit_t;

typedef struct
{
    __IO uint32_t CMPF1;
    uint32_t RESERVED0[15];
} stc_tmrb_stflr_bit_t;

typedef struct
{
    __IO uint32_t CAPMD;
    uint32_t RESERVED0[3];
    __IO uint32_t HICP0;
    __IO uint32_t HICP1;
    __IO uint32_t HICP2;
    uint32_t RESERVED1[5];
    __IO uint32_t NOFIENCP;
    __IO uint32_t NOFICKCP0;
    __IO uint32_t NOFICKCP1;
    uint32_t RESERVED2[1];
} stc_tmrb_cconr_bit_t;

typedef struct
{
    __IO uint32_t STAC0;
    __IO uint32_t STAC1;
    __IO uint32_t STPC0;
    __IO uint32_t STPC1;
    __IO uint32_t CMPC0;
    __IO uint32_t CMPC1;
    __IO uint32_t PERC0;
    __IO uint32_t PERC1;
    __IO uint32_t FORC0;
    __IO uint32_t FORC1;
    uint32_t RESERVED0[2];
    __IO uint32_t OUTEN;
    uint32_t RESERVED1[3];
} stc_tmrb_pconr_bit_t;

typedef struct
{
    __I  uint32_t PE;
    __I  uint32_t FE;
    uint32_t RESERVED0[1];
    __I  uint32_t ORE;
    uint32_t RESERVED1[1];
    __I  uint32_t RXNE;
    __I  uint32_t TC;
    __I  uint32_t TXE;
    uint32_t RESERVED2[8];
    __I  uint32_t MPB;
    uint32_t RESERVED3[15];
} stc_usart_sr_bit_t;

typedef struct
{
    uint32_t RESERVED0[9];
    __IO uint32_t MPID;
    uint32_t RESERVED1[22];
} stc_usart_dr_bit_t;

typedef struct
{
    uint32_t RESERVED0[2];
    __IO uint32_t RE;
    __IO uint32_t TE;
    __IO uint32_t SLME;
    __IO uint32_t RIE;
    __IO uint32_t TCIE;
    __IO uint32_t TXEIE;
    uint32_t RESERVED1[1];
    __IO uint32_t PS;
    __IO uint32_t PCE;
    uint32_t RESERVED2[1];
    __IO uint32_t M;
    uint32_t RESERVED3[2];
    __IO uint32_t OVER8;
    __O  uint32_t CPE;
    __O  uint32_t CFE;
    uint32_t RESERVED4[1];
    __O  uint32_t CORE;
    uint32_t RESERVED5[4];
    __IO uint32_t MS;
    uint32_t RESERVED6[3];
    __IO uint32_t ML;
    uint32_t RESERVED7[1];
    __IO uint32_t NFE;
    __IO uint32_t SBS;
} stc_usart_cr1_bit_t;

typedef struct
{
    __IO uint32_t MPE;
    uint32_t RESERVED0[10];
    __IO uint32_t CLKC0;
    __IO uint32_t CLKC1;
    __IO uint32_t STOP;
    __IO uint32_t LINEN;
    uint32_t RESERVED1[17];
} stc_usart_cr2_bit_t;

typedef struct
{
    uint32_t RESERVED0[3];
    __IO uint32_t HDSEL;
    uint32_t RESERVED1[5];
    __IO uint32_t CTSE;
    uint32_t RESERVED2[22];
} stc_usart_cr3_bit_t;

typedef struct
{
    __IO uint32_t PSC0;
    __IO uint32_t PSC1;
    uint32_t RESERVED0[30];
} stc_usart_pr_bit_t;


typedef struct
{
    stc_adc_str_bit_t                        STR_b;
    uint32_t                                 RESERVED0[8];
    stc_adc_cr0_bit_t                        CR0_b;
    stc_adc_cr1_bit_t                        CR1_b;
    uint32_t                                 RESERVED1[32];
    stc_adc_trgsr_bit_t                      TRGSR_b;
    uint32_t                                 RESERVED2[96];
    stc_adc_exchselr_bit_t                   EXCHSELR_b;
    uint32_t                                 RESERVED3[344];
    stc_adc_isr_bit_t                        ISR_b;
    stc_adc_icr_bit_t                        ICR_b;
    stc_adc_isclrr_bit_t                     ISCLRR_b;
    uint32_t                                 RESERVED4[712];
    stc_adc_awdcr_bit_t                      AWDCR_b;
    stc_adc_awdsr_bit_t                      AWDSR_b;
    stc_adc_awdsclrr_bit_t                   AWDSCLRR_b;
} bCM_ADC_TypeDef;

typedef struct
{
    stc_aos_intc_strgcr_bit_t                INTC_STRGCR_b;
} bCM_AOS_TypeDef;

typedef struct
{
    stc_cmu_pericksel_bit_t                  PERICKSEL_b;
    uint32_t                                 RESERVED0[24];
    stc_cmu_xtalstdsr_bit_t                  XTALSTDSR_b;
    uint32_t                                 RESERVED1[24];
    stc_cmu_sckdivr_bit_t                    SCKDIVR_b;
    uint32_t                                 RESERVED2[24];
    stc_cmu_ckswr_bit_t                      CKSWR_b;
    uint32_t                                 RESERVED3[24];
    stc_cmu_xtalcr_bit_t                     XTALCR_b;
    uint32_t                                 RESERVED4[24];
    stc_cmu_xtalcfgr_bit_t                   XTALCFGR_b;
    stc_cmu_xtalstbcr_bit_t                  XTALSTBCR_b;
    uint32_t                                 RESERVED5[16];
    stc_cmu_hrccr_bit_t                      HRCCR_b;
    uint32_t                                 RESERVED6[56];
    stc_cmu_oscstbsr_bit_t                   OSCSTBSR_b;
    uint32_t                                 RESERVED7[24];
    stc_cmu_mco1cfgr_bit_t                   MCO1CFGR_b;
    uint32_t                                 RESERVED8[24];
    stc_cmu_xtalstdcr_bit_t                  XTALSTDCR_b;
    uint32_t                                 RESERVED9[56];
    stc_cmu_fcg_bit_t                        FCG_b;
    stc_cmu_xtal32cr_bit_t                   XTAL32CR_b;
    uint32_t                                 RESERVED10[24];
    stc_cmu_xtal32cfgr_bit_t                 XTAL32CFGR_b;
    stc_cmu_xtal32nfr_bit_t                  XTAL32NFR_b;
    uint32_t                                 RESERVED11[16];
    stc_cmu_lrccr_bit_t                      LRCCR_b;
} bCM_CMU_TypeDef;

typedef struct
{
    stc_crc_cr_bit_t                         CR_b;
} bCM_CRC_TypeDef;

typedef struct
{
    stc_ctc_cr1_bit_t                        CR1_b;
    uint32_t                                 RESERVED0[32];
    stc_ctc_str_bit_t                        STR_b;
} bCM_CTC_TypeDef;

typedef struct
{
    stc_dbgc_mcudbgstat_bit_t                MCUDBGSTAT_b;
    stc_dbgc_mcustpctl_bit_t                 MCUSTPCTL_b;
} bCM_DBGC_TypeDef;

typedef struct
{
    uint32_t                                 RESERVED0[128];
    stc_dbgc_t_mcustat_bit_t                 MCUSTAT_b;
    stc_dbgc_t_mcuctl_bit_t                  MCUCTL_b;
    stc_dbgc_t_fmcctl_bit_t                  FMCCTL_b;
} bCM_DBGC_T_TypeDef;

typedef struct
{
    stc_dma_en_bit_t                         EN_b;
    stc_dma_intstat0_bit_t                   INTSTAT0_b;
    stc_dma_intstat1_bit_t                   INTSTAT1_b;
    stc_dma_intmask0_bit_t                   INTMASK0_b;
    stc_dma_intmask1_bit_t                   INTMASK1_b;
    stc_dma_intclr0_bit_t                    INTCLR0_b;
    stc_dma_intclr1_bit_t                    INTCLR1_b;
    stc_dma_chen_bit_t                       CHEN_b;
    uint32_t                                 RESERVED0[32];
    stc_dma_chstat_bit_t                     CHSTAT_b;
    uint32_t                                 RESERVED1[128];
    stc_dma_chenclr_bit_t                    CHENCLR_b;
    uint32_t                                 RESERVED2[96];
    stc_dma_ch0ctl0_bit_t                    CH0CTL0_b;
    stc_dma_ch0ctl1_bit_t                    CH0CTL1_b;
    uint32_t                                 RESERVED3[448];
    stc_dma_ch1ctl0_bit_t                    CH1CTL0_b;
    stc_dma_ch1ctl1_bit_t                    CH1CTL1_b;
} bCM_DMA_TypeDef;

typedef struct
{
    uint32_t                                 RESERVED0[32];
    stc_efm_fstp_bit_t                       FSTP_b;
    stc_efm_frmc_bit_t                       FRMC_b;
    stc_efm_fwmc_bit_t                       FWMC_b;
    stc_efm_fsr_bit_t                        FSR_b;
    stc_efm_fsclr_bit_t                      FSCLR_b;
    stc_efm_fite_bit_t                       FITE_b;
    uint32_t                                 RESERVED1[4912];
    stc_efm_cmu_hrccfgr_bit_t                CMU_HRCCFGR_b;
    uint32_t                                 RESERVED2[8];
    stc_efm_pwc_lvdicgcr_bit_t               PWC_LVDICGCR_b;
} bCM_EFM_TypeDef;

typedef struct
{
    stc_gpio_pidr_bit_t                      PIDR0_b;
    stc_gpio_pidr_bit_t                      PIDR1_b;
    stc_gpio_pidr_bit_t                      PIDR2_b;
    stc_gpio_pidr_bit_t                      PIDR3_b;
    stc_gpio_pidr_bit_t                      PIDR4_b;
    stc_gpio_pidr_bit_t                      PIDR5_b;
    stc_gpio_pidr_bit_t                      PIDR6_b;
    stc_gpio_pidr_bit_t                      PIDR7_b;
    uint32_t                                 RESERVED0[32];
    stc_gpio_pidr_bit_t                      PIDR12_b;
    stc_gpio_pidr_bit_t                      PIDR13_b;
    stc_gpio_pidr_bit_t                      PIDR14_b;
    uint32_t                                 RESERVED1[8];
    stc_gpio_podr_bit_t                      PODR0_b;
    stc_gpio_podr_bit_t                      PODR1_b;
    stc_gpio_podr_bit_t                      PODR2_b;
    stc_gpio_podr_bit_t                      PODR3_b;
    stc_gpio_podr_bit_t                      PODR4_b;
    stc_gpio_podr_bit_t                      PODR5_b;
    stc_gpio_podr_bit_t                      PODR6_b;
    stc_gpio_podr_bit_t                      PODR7_b;
    uint32_t                                 RESERVED2[32];
    stc_gpio_podr_bit_t                      PODR12_b;
    stc_gpio_podr_bit_t                      PODR13_b;
    stc_gpio_podr_bit_t                      PODR14_b;
    uint32_t                                 RESERVED3[8];
    stc_gpio_poer_bit_t                      POER0_b;
    stc_gpio_poer_bit_t                      POER1_b;
    stc_gpio_poer_bit_t                      POER2_b;
    stc_gpio_poer_bit_t                      POER3_b;
    stc_gpio_poer_bit_t                      POER4_b;
    stc_gpio_poer_bit_t                      POER5_b;
    stc_gpio_poer_bit_t                      POER6_b;
    stc_gpio_poer_bit_t                      POER7_b;
    uint32_t                                 RESERVED4[32];
    stc_gpio_poer_bit_t                      POER12_b;
    stc_gpio_poer_bit_t                      POER13_b;
    stc_gpio_poer_bit_t                      POER14_b;
    uint32_t                                 RESERVED5[8];
    stc_gpio_posr_bit_t                      POSR0_b;
    stc_gpio_posr_bit_t                      POSR1_b;
    stc_gpio_posr_bit_t                      POSR2_b;
    stc_gpio_posr_bit_t                      POSR3_b;
    stc_gpio_posr_bit_t                      POSR4_b;
    stc_gpio_posr_bit_t                      POSR5_b;
    stc_gpio_posr_bit_t                      POSR6_b;
    stc_gpio_posr_bit_t                      POSR7_b;
    uint32_t                                 RESERVED6[32];
    stc_gpio_posr_bit_t                      POSR12_b;
    stc_gpio_posr_bit_t                      POSR13_b;
    stc_gpio_posr_bit_t                      POSR14_b;
    uint32_t                                 RESERVED7[8];
    stc_gpio_porr_bit_t                      PORR0_b;
    stc_gpio_porr_bit_t                      PORR1_b;
    stc_gpio_porr_bit_t                      PORR2_b;
    stc_gpio_porr_bit_t                      PORR3_b;
    stc_gpio_porr_bit_t                      PORR4_b;
    stc_gpio_porr_bit_t                      PORR5_b;
    stc_gpio_porr_bit_t                      PORR6_b;
    stc_gpio_porr_bit_t                      PORR7_b;
    uint32_t                                 RESERVED8[32];
    stc_gpio_porr_bit_t                      PORR12_b;
    stc_gpio_porr_bit_t                      PORR13_b;
    stc_gpio_porr_bit_t                      PORR14_b;
    uint32_t                                 RESERVED9[8];
    stc_gpio_potr_bit_t                      POTR0_b;
    stc_gpio_potr_bit_t                      POTR1_b;
    stc_gpio_potr_bit_t                      POTR2_b;
    stc_gpio_potr_bit_t                      POTR3_b;
    stc_gpio_potr_bit_t                      POTR4_b;
    stc_gpio_potr_bit_t                      POTR5_b;
    stc_gpio_potr_bit_t                      POTR6_b;
    stc_gpio_potr_bit_t                      POTR7_b;
    uint32_t                                 RESERVED10[32];
    stc_gpio_potr_bit_t                      POTR12_b;
    stc_gpio_potr_bit_t                      POTR13_b;
    stc_gpio_potr_bit_t                      POTR14_b;
    uint32_t                                 RESERVED11[7432];
    stc_gpio_pcr_bit_t                       PCR00_b;
    stc_gpio_pcr_bit_t                       PCR01_b;
    stc_gpio_pcr_bit_t                       PCR02_b;
    stc_gpio_pcr_bit_t                       PCR03_b;
    stc_gpio_pcr_bit_t                       PCR04_b;
    stc_gpio_pcr_bit_t                       PCR05_b;
    stc_gpio_pcr_bit_t                       PCR06_b;
    uint32_t                                 RESERVED12[16];
    stc_gpio_pcr_bit_t                       PCR10_b;
    stc_gpio_pcr_bit_t                       PCR11_b;
    stc_gpio_pcr_bit_t                       PCR12_b;
    stc_gpio_pcr_bit_t                       PCR13_b;
    stc_gpio_pcr_bit_t                       PCR14_b;
    stc_gpio_pcr_bit_t                       PCR15_b;
    stc_gpio_pcr_bit_t                       PCR16_b;
    stc_gpio_pcr_bit_t                       PCR17_b;
    stc_gpio_pcr_bit_t                       PCR20_b;
    stc_gpio_pcr_bit_t                       PCR21_b;
    stc_gpio_pcr_bit_t                       PCR22_b;
    stc_gpio_pcr_bit_t                       PCR23_b;
    stc_gpio_pcr_bit_t                       PCR24_b;
    stc_gpio_pcr_bit_t                       PCR25_b;
    stc_gpio_pcr_bit_t                       PCR26_b;
    stc_gpio_pcr_bit_t                       PCR27_b;
    stc_gpio_pcr_bit_t                       PCR30_b;
    stc_gpio_pcr_bit_t                       PCR31_b;
    uint32_t                                 RESERVED13[96];
    stc_gpio_pcr_bit_t                       PCR40_b;
    stc_gpio_pcr_bit_t                       PCR41_b;
    stc_gpio_pcr_bit_t                       PCR42_b;
    stc_gpio_pcr_bit_t                       PCR43_b;
    uint32_t                                 RESERVED14[64];
    stc_gpio_pcr_bit_t                       PCR50_b;
    stc_gpio_pcr_bit_t                       PCR51_b;
    stc_gpio_pcr_bit_t                       PCR52_b;
    stc_gpio_pcr_bit_t                       PCR53_b;
    stc_gpio_pcr_bit_t                       PCR54_b;
    stc_gpio_pcr_bit_t                       PCR55_b;
    uint32_t                                 RESERVED15[32];
    stc_gpio_pcr_bit_t                       PCR60_b;
    stc_gpio_pcr_bit_t                       PCR61_b;
    stc_gpio_pcr_bit_t                       PCR62_b;
    stc_gpio_pcr_bit_t                       PCR63_b;
    uint32_t                                 RESERVED16[64];
    stc_gpio_pcr_bit_t                       PCR70_b;
    stc_gpio_pcr_bit_t                       PCR71_b;
    stc_gpio_pcr_bit_t                       PCR72_b;
    stc_gpio_pcr_bit_t                       PCR73_b;
    stc_gpio_pcr_bit_t                       PCR74_b;
    stc_gpio_pcr_bit_t                       PCR75_b;
    stc_gpio_pcr_bit_t                       PCR76_b;
    stc_gpio_pcr_bit_t                       PCR77_b;
    uint32_t                                 RESERVED17[512];
    stc_gpio_pcr_bit_t                       PCR120_b;
    stc_gpio_pcr_bit_t                       PCR121_b;
    stc_gpio_pcr_bit_t                       PCR122_b;
    stc_gpio_pcr_bit_t                       PCR123_b;
    stc_gpio_pcr_bit_t                       PCR124_b;
    uint32_t                                 RESERVED18[48];
    stc_gpio_pcr_bit_t                       PCR130_b;
    uint32_t                                 RESERVED19[96];
    stc_gpio_pcr_bit_t                       PCR137_b;
    stc_gpio_pcr_bit_t                       PCR140_b;
    stc_gpio_pcr_bit_t                       PCR141_b;
    uint32_t                                 RESERVED20[64];
    stc_gpio_pcr_bit_t                       PCR146_b;
    stc_gpio_pcr_bit_t                       PCR147_b;
    uint32_t                                 RESERVED21[128];
    stc_gpio_pspcr_bit_t                     PSPCR_b;
    uint32_t                                 RESERVED22[16];
    stc_gpio_pccr_bit_t                      PCCR_b;
    stc_gpio_pinaer_bit_t                    PINAER_b;
    stc_gpio_pwpr_bit_t                      PWPR_b;
} bCM_GPIO_TypeDef;

typedef struct
{
    stc_i2c_cr1_bit_t                        CR1_b;
    stc_i2c_cr2_bit_t                        CR2_b;
    uint32_t                                 RESERVED0[64];
    stc_i2c_slr0_bit_t                       SLR0_b;
    stc_i2c_slr1_bit_t                       SLR1_b;
    uint32_t                                 RESERVED1[32];
    stc_i2c_sr_bit_t                         SR_b;
    stc_i2c_clr_bit_t                        CLR_b;
    uint32_t                                 RESERVED2[64];
    stc_i2c_ccr_bit_t                        CCR_b;
    stc_i2c_fltr_bit_t                       FLTR_b;
} bCM_I2C_TypeDef;

typedef struct
{
    stc_icg_icg0_bit_t                       ICG0_b;
    stc_icg_icg1_bit_t                       ICG1_b;
} bCM_ICG_TypeDef;

typedef struct
{
    uint32_t                                 RESERVED0[32];
    stc_intc_nmier_bit_t                     NMIER_b;
    stc_intc_nmifr_bit_t                     NMIFR_b;
    stc_intc_nmiclr_bit_t                    NMICLR_b;
    uint32_t                                 RESERVED1[128];
    stc_intc_evter_bit_t                     EVTER_b;
    stc_intc_ekeycr_bit_t                    EKEYCR_b;
    uint32_t                                 RESERVED2[160];
    stc_intc_fprcr_bit_t                     FPRCR_b;
    stc_intc_eirqcr_bit_t                    EIRQCR0_b;
    stc_intc_eirqcr_bit_t                    EIRQCR1_b;
    stc_intc_eirqcr_bit_t                    EIRQCR2_b;
    stc_intc_eirqcr_bit_t                    EIRQCR3_b;
    stc_intc_eirqcr_bit_t                    EIRQCR4_b;
    stc_intc_eirqcr_bit_t                    EIRQCR5_b;
    stc_intc_eirqcr_bit_t                    EIRQCR6_b;
    stc_intc_eirqcr_bit_t                    EIRQCR7_b;
    stc_intc_eirqcr_bit_t                    EIRQCR8_b;
    stc_intc_eirqcr_bit_t                    EIRQCR9_b;
    stc_intc_eirqcr_bit_t                    EIRQCR10_b;
    stc_intc_eirqcr_bit_t                    EIRQCR11_b;
    stc_intc_wupenr_bit_t                    WUPENR_b;
    stc_intc_eirqfr_bit_t                    EIRQFR_b;
    stc_intc_eirqclr_bit_t                   EIRQCLR_b;
    uint32_t                                 RESERVED3[800];
    stc_intc_iselbr_bit_t                    ISELBR24_b;
    stc_intc_iselbr_bit_t                    ISELBR25_b;
    stc_intc_iselbr_bit_t                    ISELBR26_b;
    stc_intc_iselbr_bit_t                    ISELBR27_b;
    stc_intc_iselbr_bit_t                    ISELBR28_b;
    stc_intc_iselbr_bit_t                    ISELBR29_b;
    stc_intc_iselbr_bit_t                    ISELBR30_b;
    stc_intc_iselbr_bit_t                    ISELBR31_b;
} bCM_INTC_TypeDef;

typedef struct
{
    stc_pwc_stpmcr_bit_t                     STPMCR_b;
    uint32_t                                 RESERVED0[24];
    stc_pwc_pwrc_bit_t                       PWRC_b;
    uint32_t                                 RESERVED1[24];
    stc_pwc_pwrmon_bit_t                     PWRMON_b;
    uint32_t                                 RESERVED2[24];
    stc_pwc_ramcr_bit_t                      RAMCR_b;
    uint32_t                                 RESERVED3[24];
    stc_pwc_lvdcsr_bit_t                     LVDCSR_b;
    uint32_t                                 RESERVED4[120];
    stc_pwc_fprc_bit_t                       FPRC_b;
    uint32_t                                 RESERVED5[240];
    stc_pwc_dbgc_bit_t                       DBGC_b;
} bCM_PWC_TypeDef;

typedef struct
{
    stc_rmu_rstf0_bit_t                      RSTF0_b;
} bCM_RMU_TypeDef;

typedef struct
{
    stc_rtc_cr0_bit_t                        CR0_b;
    uint32_t                                 RESERVED0[24];
    stc_rtc_cr1_bit_t                        CR1_b;
    uint32_t                                 RESERVED1[24];
    stc_rtc_cr2_bit_t                        CR2_b;
    uint32_t                                 RESERVED2[24];
    stc_rtc_cr3_bit_t                        CR3_b;
    uint32_t                                 RESERVED3[88];
    stc_rtc_hour_bit_t                       HOUR_b;
    uint32_t                                 RESERVED4[184];
    stc_rtc_almhour_bit_t                    ALMHOUR_b;
    uint32_t                                 RESERVED5[24];
    stc_rtc_almweek_bit_t                    ALMWEEK_b;
    uint32_t                                 RESERVED6[24];
    stc_rtc_errcrh_bit_t                     ERRCRH_b;
} bCM_RTC_TypeDef;

typedef struct
{
    uint32_t                                 RESERVED0[32];
    stc_spi_cr1_bit_t                        CR1_b;
    uint32_t                                 RESERVED1[32];
    stc_spi_cfg1_bit_t                       CFG1_b;
    uint32_t                                 RESERVED2[32];
    stc_spi_sr_bit_t                         SR_b;
    stc_spi_cfg2_bit_t                       CFG2_b;
} bCM_SPI_TypeDef;

typedef struct
{
    stc_swdt_cr_bit_t                        CR_b;
    stc_swdt_sr_bit_t                        SR_b;
} bCM_SWDT_TypeDef;

typedef struct
{
    uint32_t                                 RESERVED0[128];
    stc_tmr0_bconr_bit_t                     BCONR_b;
    stc_tmr0_stflr_bit_t                     STFLR_b;
} bCM_TMR0_TypeDef;

typedef struct
{
    uint32_t                                 RESERVED0[1024];
    stc_tmrb_bcstr_bit_t                     BCSTR_b;
    uint32_t                                 RESERVED1[16];
    stc_tmrb_hconr_bit_t                     HCONR_b;
    uint32_t                                 RESERVED2[16];
    stc_tmrb_hcupr_bit_t                     HCUPR_b;
    uint32_t                                 RESERVED3[16];
    stc_tmrb_hcdor_bit_t                     HCDOR_b;
    uint32_t                                 RESERVED4[16];
    stc_tmrb_iconr_bit_t                     ICONR_b;
    uint32_t                                 RESERVED5[16];
    stc_tmrb_econr_bit_t                     ECONR_b;
    uint32_t                                 RESERVED6[48];
    stc_tmrb_stflr_bit_t                     STFLR_b;
    uint32_t                                 RESERVED7[784];
    stc_tmrb_cconr_bit_t                     CCONR_b;
    uint32_t                                 RESERVED8[496];
    stc_tmrb_pconr_bit_t                     PCONR_b;
} bCM_TMRB_TypeDef;

typedef struct
{
    stc_usart_sr_bit_t                       SR_b;
    stc_usart_dr_bit_t                       DR_b;
    uint32_t                                 RESERVED0[32];
    stc_usart_cr1_bit_t                      CR1_b;
    stc_usart_cr2_bit_t                      CR2_b;
    stc_usart_cr3_bit_t                      CR3_b;
    stc_usart_pr_bit_t                       PR_b;
} bCM_USART_TypeDef;


/******************************************************************************/
/*      Device Specific Peripheral bit_band declaration & memory map          */
/******************************************************************************/

#define bCM_ADC                              ((bCM_ADC_TypeDef *)0x42170000UL)
#define bCM_AOS                              ((bCM_AOS_TypeDef *)0x42018000UL)
#define bCM_CMU                              ((bCM_CMU_TypeDef *)0x42288000UL)
#define bCM_CRC                              ((bCM_CRC_TypeDef *)0x422A8000UL)
#define bCM_CTC                              ((bCM_CTC_TypeDef *)0x42000000UL)
#define bCM_DBGC                             ((bCM_DBGC_TypeDef *)0x422A0000UL)
#define bCM_DMA                              ((bCM_DMA_TypeDef *)0x42260000UL)
#define bCM_EFM                              ((bCM_EFM_TypeDef *)0x42010000UL)
#define bCM_GPIO                             ((bCM_GPIO_TypeDef *)0x42270000UL)
#define bCM_I2C                              ((bCM_I2C_TypeDef *)0x42090000UL)
#define bCM_INTC                             ((bCM_INTC_TypeDef *)0x42220000UL)
#define bCM_PWC                              ((bCM_PWC_TypeDef *)0x42280000UL)
#define bCM_RMU                              ((bCM_RMU_TypeDef *)0x42282000UL)
#define bCM_RTC                              ((bCM_RTC_TypeDef *)0x421A8000UL)
#define bCM_SPI                              ((bCM_SPI_TypeDef *)0x42070000UL)
#define bCM_SWDT                             ((bCM_SWDT_TypeDef *)0x42198000UL)
#define bCM_TMR0                             ((bCM_TMR0_TypeDef *)0x420B0000UL)
#define bCM_TMRB_1                           ((bCM_TMRB_TypeDef *)0x420F0000UL)
#define bCM_TMRB_2                           ((bCM_TMRB_TypeDef *)0x420F8000UL)
#define bCM_TMRB_3                           ((bCM_TMRB_TypeDef *)0x42100000UL)
#define bCM_TMRB_4                           ((bCM_TMRB_TypeDef *)0x42108000UL)
#define bCM_TMRB_5                           ((bCM_TMRB_TypeDef *)0x42110000UL)
#define bCM_TMRB_6                           ((bCM_TMRB_TypeDef *)0x42118000UL)
#define bCM_TMRB_7                           ((bCM_TMRB_TypeDef *)0x42120000UL)
#define bCM_TMRB_8                           ((bCM_TMRB_TypeDef *)0x42128000UL)
#define bCM_USART1                           ((bCM_USART_TypeDef *)0x42030000UL)
#define bCM_USART2                           ((bCM_USART_TypeDef *)0x42038000UL)
#define bCM_USART3                           ((bCM_USART_TypeDef *)0x42040000UL)
#define bCM_USART4                           ((bCM_USART_TypeDef *)0x42048000UL)
#define bCM_USART5                           ((bCM_USART_TypeDef *)0x42050000UL)
#define bCM_USART6                           ((bCM_USART_TypeDef *)0x42058000UL)



#ifdef __cplusplus
}
#endif

#endif /* __HC32F160_H__ */


